Abstract: A new approach is proposed that contemplates systems and methods to support a mechanism to offload all aspects of inline SSL processing of an application running on a server/host to an embedded networking device such as a Network Interface Card (NIC), which serves as a hardware accelerator for all applications running on the server that need to have a secure connection with a remote client device over a network. By utilizing a plurality of its software and hardware features, the embedded networking device is configured to process all SSL operations of the secure connection inline, i.e., the SSL operations are performed as packets are transferred between the host and the client over the network, rather than having the SSL operations offloaded to the NIC, which then returns the packets to the host (or the remote client device) before they can be transmitted to the remote client device (or to the host).

Abstract: Methods and apparatus for calculating TB CRC values. In an exemplary embodiment, a method includes receiving code blocks (CBs) that form code block groups (CBGs), which form a transport block (TB), generating partial TB cyclic redundancy check (CRC) values from the CBGs, and processing the partial TB CRC values to determine a full TB CRC value. The method also includes comparing the full TB CRC value to a received TB CRC value to determine if the TB has been successfully received. An apparatus includes a receiver that receives code blocks (CBs) that form a transport block (TB), and a generator that generates partial TB CRC values from the CBGs. The apparatus also includes a TB CRC checker that processes the partial TB CRC values to determine a full TB CRC value that is compared to a received TB CRC value to determine if the TB has been successfully received.

Abstract: A network switch to support scalable and flexible wildcard matching (WCM) comprises a packet processing pipeline including a plurality of packet processing units each configured to generate a master key for a WCM request to a memory pool and process a packet based on looked up WCM rules. The memory pool includes a plurality of memory groups each configured to maintain a plurality of WCM tables to be searched in one or more SRAM memory tiles of the memory group, format the master key generated by the packet processing unit into a compact key based on a bitmap per user configuration, hash the formatted compact key and perform wildcard matching with the WCM tables stored in the one or more SRAM memory tiles of the memory group using the formatted compact key, process and provide the WCM rules from the wildcard matching to the requesting packet processing unit.

Abstract: A system, apparatus, and method are provided for adding, deleting, and modifying rules in one update from the perspective of an active search process for packet classification. While a search processor searches for one or more rules that match keys generated from received packets, there is a need to add, delete, or modify rules. By organizing a plurality incremental updates for adding, deleting, or modifying rules into a batch update, several operations for incorporating the incremental updates may be made more efficient by minimizing a number of updates required.

Abstract: A testbench for testing a device under test (DUT), wherein the testbench has a verification environment including a reference model, a scoreboard and a customized agent for each interface that the DUT needs to receive input from and/or transmit output on. The testbench system is able to be generated by a testbench builder that automatically creates a scoreboard, a reference model, a dispatcher and generic agents including generic drivers, loopback ports, sequencers and/or generic monitors for each interface and then automatically customize the generic agents based on their corresponding interface such that the agents meet the requirements of the interface for the DUT.

Abstract: A new approach is proposed that contemplates systems and methods to support hardware-based Quality of Service (QoS) operations, which offloads metering functionalities under OpenFlow protocol to a programmable hardware unit/block/component. The hardware unit supports several hardware implemented ports and each port supports multiple configurable queues for the packet flows through a network switch/chip/system. Specifically, the hardware unit includes a plurality of descriptor queues (DQs) configured to accept requests to send a plurality of packets from one or more CPU cores, and a plurality of condition and schedule modules configured to meter, schedule, and condition the packets through a hierarchy of scheduling queues under one or more metering constraints.

Abstract: Embodiments of the present invention are directed to a multiple-interrupt propagation scheme, which is an automated mechanism for the specification and creation of interrupts. Interrupts originating at leaf nodes of a network chip are categorized into different service levels according to their interrupt types and are propagated to a master of the network chip via a manager. For each interrupt, depending on its service level, the manager either instantaneously propagates the interrupt or delays propagation of the interrupt to the master. The master forwards the interrupts to different destinations. A destination can be a processing element that is located on the network chip or externally on a different chip.

Abstract: In an embodiment, interfacing a pipeline with two or more interfaces in a hardware processor includes providing a single pipeline in a hardware processor. The single pipeline presents at least two visible units. The single pipeline includes replicated architecturally visible structures, shared logic resources, and shared architecturally hidden structures. The method further includes receiving a request from one of a plurality of interfaces at one of the visible units. The method also includes tagging the request with an identifier based on the one of the at least two visible units that received the request. The method further includes processing the request in the single pipeline by propagating the request through the single pipeline through the replicated architecturally visible structures that correspond with the identifier.

Abstract: A packet processing system having a control path memory of a control path subsystem and a datapath memory of a datapath subsystem. The datapath subsystem stores packet data of incoming packets and the control path subsystem performs matches of a subset of packet data, or a hash of the packet data, against the contents of a the control path memory in order to process the packets. The packet processing system enabling a portion of the datapath memory to be used by the control subsystem if needed or a portion of the control path memory to be used by the datapath subsystem if needed.

Abstract: One aspect of the present invention discloses a network system capable of transmitting and processing audio video (“A/V”) data with enhanced quality of service (“QoS”). The network system includes a transmitter, a transmission channel, an adjustable decoder buffer, and a decoder. The transmitter contains an encoder able to encode A/V data in accordance with encoding bit rate recommendation from SQoS and packets loss notifications. The transmission channel, in one example, transmits A/V data from the transmitter or the receiver. The adjustable decoder buffer, in one aspect, is able to change its storage capacity or buffering size in response to the adaptive latency estimate. Upon fetching at least a portion of the A/V data from the adjustable decoder buffer, SQoS updates the adaptive latency estimate based on the quality of the decoded A/V data.

Abstract: A level-up shifter circuit is suitable for high speed and low power applications. The circuit dissipates almost no static power, or leakage current, compared to conventional designs and can preserve the signal's duty cycle even at high data rates. This circuit can be used with a wide range of power supplies while maintaining operational integrity, and includes circuitry to compensate for process variations.

Abstract: Embodiments of the apparatus for reducing latency in a flexible parser relate to an implementation that optimizes each parser engine within the parser. A packet enters the parser. Each of the parser engines processes the packet if processing is required. Otherwise, the parser engine simply forwards the packet through without processing the packet, thereby reducing latency. Each parser engine includes a memory. The memory stores bypass data and status information that indicates whether parsing for this packet is completed and, thus, no further processing is required by subsequent parser engines. Each parser engine also includes a counter, which is incremented whenever a packet enters the parser engine and is decremented whenever a packet exists the parser engine. A packet bypasses the parser engine based on the counter of the parser engine and the status information of that packet.

Abstract: A method of managing a buffer (or buffer memory) includes utilizing one or more shared pool buffers, one or more port/priority buffers and a global multicast pool. When packets are received, a shared pool buffer is utilized; however, if a packet does not fit in the shared pool buffer, then the appropriate port/priority buffer is used. If the packet is a multicast packet, then the global multicast pool is utilized for copies of the packet.

Abstract: A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache. Further, a collapsed TLB provides an additional cache storing collapsed translations derived from the MTLB.

Abstract: Embodiments of the present invention relate to an architecture that uses hierarchical statistically multiplexed counters to extend counter life by orders of magnitude. Each level includes statistically multiplexed counters. The statistically multiplexed counters includes P base counters and S subcounters, wherein the S subcounters are dynamically concatenated with the P base counters. When a row overflow in a level occurs, counters in a next level above are used to extend counter life. The hierarchical statistically multiplexed counters can be used with an overflow FIFO to further extend counter life.

Abstract: A new approach is proposed to offload of link aggregation from a host to a HBA in SRIOV mode. The HBA first creates one or more link aggregation offload engines each having one or more physical ports and to establish a first link between a VM running on the host and one of the link aggregation offload engines for network data transmission with the VM. Once a data packet is received from the VM over the first link, the link aggregation offload engine chooses a first physical port based on its link aggregation method and establish a second link with the chosen first physical port to transmit the packet out of the HBA. If the second link fails, the link aggregation offload engine then chooses a second physical ports and establish a third link with the chosen second physical port to transmit the packet out of the HBA device instead.

Abstract: Methods and apparatuses for providing soft and blind combining for PUSCH CQI processing are disclosed. In an exemplary embodiment, a method includes generating a plurality of hypothetical rank indicator (RI) values associated with a user equipment (UE), and concurrently soft-combining channel quality information (CQI) and RI information associated with the UE that is contained in a received subframe of symbols. The RI information is soft-combined to generate a soft-combined RI bit stream and the CQI information is soft-combined based on the plurality of hypothetical RI values to generate a plurality of soft-combined CQI bit streams, respectively. The method also includes decoding the soft-combined RI bit stream to generate a decoded RI value, and decoding a selected soft-combined CQI bit stream based on the decoded RI value to generate a decoded CQI value.

Abstract: Methods and systems for network devices are provided. One method includes receiving a serial data stream at a network interface of a network device coupled to a network link to communicate with other networked devices, the data stream including an alignment marker with a bit pattern for recovering a bit stream used by network device logic for processing the received serial data stream; using a plurality of comparators for simultaneously comparing within a single clock cycle, portions of a parallel data stream generated after converting the serial data stream by a de-serializer of the network device; detecting the bit pattern of the alignment marker in the parallel data stream by one of the plurality of comparators; storing a starting bit position of the alignment marker in the parallel data stream; and reordering the parallel data stream based on the stored starting bit position of the alignment marker.

Abstract: Machine implemented methods and systems for writing data at a storage device are provided. A write command from an initiator adapter is received at a target adapter interfacing with a target controller for writing data to the storage device; where the write command includes information regarding a virtual logical unit number (LUN) for writing data in response to the write command. The target controller uses an indicator to notify the target adapter to process the write command and provides information regarding a designated LUN for the storage device where data is to be written at the storage device in response to the write command. Thereafter, the target adapter sends a response to the initiator adapter that it is ready to receive data and issues a write command for the storage device at the same time.

Abstract: Address translation and caching is managed using a processor that includes at least one CPU configured to run a hypervisor at a first access level and at least one guest operating system at a second access level. The managing includes: at the second access level, translating from virtual addresses to intermediate physical; at the second access level, determining reuse information for ranges of virtual addresses based on estimated reuse of data stored within a virtual address space; at the first access level, translating from the intermediate physical addresses to physical addresses; at the first access level, determining reuse information for ranges of intermediate physical addresses based on estimated reuse of data stored within an intermediate physical address space; and processing reuse information determined at different access levels to store cache lines in selected portions of a first cache.