Abstract: A network lookup engine in a network switch is configured to generate multiple lookup queries for each incoming packet in parallel to a remote search engine. The number and type of the lookup queries depend on the protocols supported by the network switch. The responses from the search engine arriving at the lookup engine are not in the same order as the order of the packets. The network lookup engine is configured to collect the responses for the parallel lookup queries in two modes: 1) in-order mode in which the first packet having its lookup queries sent to the search engine has its responses collected first regardless of the order of the responses received from the search engine; 2) out-of-order mode in which the first packet having complete responses to its lookup queries from the search engine has its responses collected first regardless of the order of incoming packets.

Abstract: Methods and apparatus for adaptive power profiling in a baseband processing system. In an exemplary embodiment, an apparatus includes one or more processing engines. Each processing engine performs at least one data processing function. The apparatus also includes an adaptive power profile (APP) and a job manager that receives job requests for data processing. The job manager allocates the data processing associated with the job requests to the processing engines based on the adaptive power profile. The adaptive power profile identifies a first group of the processing engines to perform the data processing associated with the job requests, and identifies remaining processing engines to be set to a low power mode.

Abstract: A new approach is proposed to support monitoring Perfect Forward Secrecy (PFS) network traffic by utilizing a hardware security module (HSM) appliance. Here, the HSM appliance is a high-performance, Federal Information Processing Standards (FIPS) 140-compliant security hardware with embedded firmware, which can be used for management and sharing of ephemeral keys used in a secured PFS communication session between two parties. Specifically, the HSM allows a server to share one or more of its ephemeral keys and/or parameters used in PFS traffic during the session with a third party under specified access rights and/or authorization, wherein the third party can be but is not limited to a traffic monitoring module. The HSM allows the third party to access the ephemeral keys stored on the HSM under the specified access rights and/or authorization so that the third party may decrypt and run analytics on the PFS traffic captured during the session.

Abstract: Methods and systems for securing data are provided. For example, one method includes receiving at an adapter, data with a first type of error protection code from a host memory of a computing device; adding by the adapter a second type of error protection code to the data before removing the first type of error protection code; generating by the adapter, a frame header for the data with a protocol specific protection code and a third type of error protection code, where the third type of error protection code is generated without using any frame header field; encrypting by the adapter, the data, the protocol specific protection code and the third type of error protection code; and transmitting by the adapter, the encrypted data with encrypted protocol specific protection code and encrypted third type of error protection code to a receiving adapter coupled to the adapter by a network link.

Abstract: A forwarding pipeline of a forwarding engine includes a mirror bit mask vector with one bit per supported independent mirror session. Each bit in the mirror bit mask vector can be set at any point in the forwarding pipeline when the forwarding engine determines that conditions for a corresponding mirror session are met. At the end of the forwarding pipeline, if any of the bits in the mirror bit mask vector is set, then a packet, the mirror bit mask vector and a pointer to the start of a mirror destination linked list are forwarded to the multicast replication engine. The mirror destination linked list typically defines a rule for mirroring. The multicast replication engine mirrors the packet according to the mirror destination linked list and the mirror bit mask vector.

Abstract: A forwarding database cache system is described herein. The forwarding database cache system includes a main forwarding database and one or more forwarding database caches. When a packet is received, the cache is searched first for information such as address information, and if found, then the packet is forwarded to the appropriate destination. If the address information is not found in the cache, then the main forwarding database is searched, and the packet is forwarded to the appropriate destination based on the information in the main forwarding database.

Abstract: A hardware-based programmable text analytics processor has a plurality of components including at least a tokenizer, a tagger, a parser, and a classifier. The tokenizer processes an input stream of unstructured text data and identifies a sequence of tokens along with their associated token ids. The tagger assigns a tag to each of the sequence of tokens from the tokenizer using a trained machine learning model. The parser parses the tagged tokens from the tagger and creates a parse tree for the tagged tokens via a plurality of shift, reduce and/or finalize transitions based on a trained machine learning model. The classifier performs classification for tagging and parsing by accepting features extracted by the tagger and the parser, classifying the features and returning classes of the features back to the tagger and the parser, respectively. The TAP then outputs structured data to be processed for various text analytics processing applications.

Abstract: In an embodiment an interface unit includes a transmit pipeline configured to transmit egress data, and a receive pipeline configured to receive ingress data. At least one of the transmit pipeline and the receive pipeline being may be configured to provide shared resources to a plurality of ports. The shared resources may include at least one of a data path resource and a control logic resource.

Abstract: Methods and systems are disclosed for routing and distributing interrupts in a multi-processor computer to various processing elements within the computer. A system for distributing the interrupts may include a plurality of logic devices configured in a hierarchical tree structure that distributes incoming interrupts to interrupt redistributors (redistribution devices). The system also includes plural processing elements, where each processing element has an associated bus address. A shared serial bus couples the redistribution devices and processing elements. Each of the redistribution devices is configured to transfer the incoming interrupts to at least one of the processing elements over the common bus, based on the bus address.

Abstract: Embodiments of the apparatus of identifying internal destinations of network packets relate to a network chip that allows flexibility in handling packets. The handling of packets can be a function of what the packet contents are or where the packets are from. The handling of packets can also be a function of both what the packet contents are and where the packets are from. In some embodiments, where the packets are from refers to unique port numbers of chip ports that the packets arrived at. The packets can be distributed for processing within the network chip.

Abstract: In an exemplary embodiment, a method for calculating transport block (TB) cyclic redundancy check (CRC) values includes receiving code blocks (CBs) that form code block groups (CBGs), which form a TB, generating partial TB CRC values from the CBGs, and processing the partial TB CRC values to determine a full TB CRC value. The method also includes comparing the full TB CRC value to a received TB CRC value to determine if the TB has been successfully received. An apparatus includes a receiver that receives CBs that form a TB, and a generator that generates partial TB CRC values from the CBGs. The apparatus also includes a TB CRC checker that processes the partial TB CRC values to determine a full TB CRC value that is compared to a received TB CRC value to determine if the TB has been successfully received.

Abstract: Methods and apparatus for coordinated multipoint receiver processing acceleration and latency reduction. In an exemplary embodiment, an apparatus includes a receiver that receives symbols from a wireless transmission and stores the symbols in a memory. The receiver also outputs an indicator that indicates that storage of the symbols in the memory has begun. The apparatus also includes a controller that outputs control signaling in response to the indicator. The apparatus also includes a link that acquires the symbols and remote scheduling and control information (RSCI) from the memory in response to receiving the control signaling. The link combines the symbols with the RSCI to form packets and transmits the packets to an external system.

Abstract: Methods and apparatus for frequency offset estimation are disclosed. In an exemplary embodiment, a method includes determining a demodulation reference signal (DMRS) frequency offset estimate from DMRS symbols in a received signal, and determining a cyclic prefix (CP) frequency offset estimate from cyclic prefix values in the received signal. The method also includes combining the DMRS and CP frequency offset estimates to determine a final frequency offset estimate. In an exemplary embodiment, an apparatus includes a DMRS frequency offset estimator that determines a DMRS frequency offset estimate based on DMRS symbols received in an uplink transmission, and a cyclic prefix (CP) frequency offset estimator that determines a CP frequency offset estimate based on cyclic prefix values in the uplink transmission. The apparatus also includes an offset combiner that combines the DMRS frequency offset estimate with the CP frequency offset estimate to generate a final frequency offset estimate.

Abstract: Twiddle factor generation for use with a programmable mix-radix vector processor (“PVP”) capable of calculating discrete Fourier transform (“DFT/IDFT”) values. In an exemplary embodiment, an apparatus includes look-up table logic that receives twiddle control factors and outputs a selected twiddle factor scaler value (TFSV), a base vector generator that generates a base vector values based on the selected TFSV, and a twiddle column generator that generates a twiddle vector from the base vector.

Abstract: A multicast destination table contains a list of links. The list of links includes the main link that is currently in use and alternate links to reach the same destination. The links in the list of links are ordered based on a metric. Each of the links is stored as an entry in the multicast destination table. A multicast replication engine traverses the list of links until an enabled link in the list of links is reached, and replicates a packet according to data associated with the enabled link in the list of links.

Abstract: Execution of the memory instructions is managed using memory management circuitry including a first cache that stores a plurality of the mappings in the page table, and a second cache that stores entries based on virtual addresses. The memory management circuitry executes operations from the one or more modules, including, in response to a first operation that invalidates at least a first virtual address, selectively ordering each of a plurality of in progress operations that were in progress when the first operation was received by the memory management circuitry, wherein a position in the ordering of a particular in progress operation depends on either or both of: (1) which of one or more modules initiated the particular in progress operation, or (2) whether or not the particular in progress operation provides results to the first cache or second cache.

Abstract: Managing lock and unlock operations for a first thread executing on a first processor core includes, for each instruction included in the first thread and identified as being associated with: (1) a lock operation corresponding to a particular lock stored in a particular memory location, in response to determining that the particular lock has already been acquired, continuing to perform the lock operation for multiple attempts using associated operation messages for accessing the particular memory location, or (2) an unlock operation corresponding to a particular lock stored in a particular memory location, releasing the particular lock from the first thread using an associated operation message for accessing the particular memory location. Selected operation messages associated with an unlock operation are prioritized over operation messages associated with a lock operation.

Abstract: A vector memory subsystem for use with a programmable mix-radix vector processor (“PVP”) capable of calculating discrete Fourier transform (“DFT/IDFT”) values. In an exemplary embodiment, an apparatus includes a vector memory bank and a vector memory system (VMS) that generates input memory addresses that are used to store input data into the vector memory bank. The VMS also generates output memory addresses that are used to unload vector data from the memory banks. The input memory addresses are used to shuffle the input data in the memory bank based on a radix factorization associated with an N-point DFT, and the output memory addresses are used to unload the vector data from the memory bank to compute radix factors of the radix factorization.

Abstract: A vector memory subsystem for use with a programmable mix-radix vector processor (“PVP”) capable of calculating discrete Fourier transform (“DFT/IDFT”) values. In an exemplary embodiment, an apparatus includes a vector memory bank and a vector memory system (VMS) that generates input memory addresses that are used to store input data into the vector memory bank. The VMS also generates output memory addresses that are used to unload vector data from the memory banks. The input memory addresses are used to shuffle the input data in the memory bank based on a radix factorization associated with an N-point DFT, and the output memory addresses are used to unload the vector data from the memory bank to compute radix factors of the radix factorization.

Abstract: A data recovery circuit provides compensation for baseline wander exhibited by a data signal. An adaptive equalizer generates a recovered data signal from a data input. A level shifter and low-pass filter provide a compensation signal as a function of the recovered data signal. An adaptation engine adjusts the level of the compensation signal to compensate for baseline wander. The adaptive equalizer generates the recovered data signal as a function of the data input and the compensation signal, thereby providing accurate recovery of the data signal.