Abstract: An array substrate of a fringe field switching (FFS) mode liquid crystal display (LCD) panel and manufacturing method thereof are provided. The gate electrodes and the common electrode of the FFS mode LCD panel are formed on the array substrate by the same photolithographic process, and the common electrode, the gate lines and the gate electrodes are disposed on the same layer. The passivation layer of the FFS mode LCD panel is formed on the pixel electrodes. The passivation layer has a plurality of first openings, and each of the first openings at least partially exposes the pixel electrodes.

Abstract: A repair method for an array substrate of a liquid crystal display device includes, providing an array substrate for a liquid crystal display device, detecting a line defect of a signal transmitting wire and locating the line defect, performing a removal process to remove a shielding layer covering two ends of the line defect and the shielding layer extending to a common line adjacent to the line defect, performing a deposition process to deposit a connecting metal layer the region where the shielding layer is removed, and performing a cutting process to cut outer ends of the common line adjacent to the line defect to form a common line section. The signal transmitting wire forms an electrical circuit with the common line section.

Abstract: Disclosed is a method of manufacturing a storage capacitor having increased aperture ratio: providing a substrate having a metal layer disposed thereon, and said metal layer is covered correspondingly with a first dielectric layer and a second dielectric layer in sequence; forming a photoresist layer with a uniform thickness to cover said second dielectric layer; performing a process of exposure-to-light and development to a portion of said photoresist layer that is correspondingly disposed over said metal layer sequentially, so that its thickness is less than its original thickness; removing said photoresist layer and etching said portion of said second dielectric layer, so that a thickness of said portion of said second dielectric layer is less than its original thickness, and the etching depth of said portion is greater than that of the other remaining portions of said second dielectric layer; and forming an electrode layer on said second dielectric layer.

Abstract: The present invention provides a display panel including a plurality of dual-gate pixel units connected to each other through data lines, gate lines and common lines. Each dual-gate pixel unit includes a first pixel and a second pixel respectively connected to a first gate line and a second gate line, and shares a common line and a data line. The first pixel and the second pixel are respectively disposed at two opposite sides of the common line, and they are also respectively disposed at two opposite sides of the first data line and the second gate line. The data lines transfer data signals into pixels, and the gate lines control the pixels to receive the data signals. The present invention raises an aperture ratio of each pixel of the display panel, and reduces the probability of the gate line and the common line being short-circuited.

Abstract: A method of manufacturing a multi-touch LCD panel. A conductive colloidal mixture formed by mixing a plurality of conductive particles and a colloid is coated on the electrode layer of the counter substrate and is solidified to make the conductive particles electrically connect to the corresponding sensing electrodes of the array substrate. Consequently, when an external force is applied to one touching position on the counter substrate, the conductive particles electrically connect the sensing electrodes to the electrode layer and the touching signal of the position can be obtained. Due to the integration of the conductive particles into the liquid crystal cell gap, the multi-touch LCD panel has the advantages of slimness and lightness. Moreover, the manufacturing process of the conductive particles is introduced after the conventional counter substrate manufacturing method, and the objective of simple process, low cost and high yields can be achieved.

Abstract: A pixel electrode structure includes a transparent substrate, a data line, a common line, a first array pixel, and a second array pixel disposed on the transparent substrate. The first/second array pixels respectively include a thin film transistor, a pixel electrode, and a gate line, and the common line is disposed at a lateral side of the gate line. A first via hole and a second via hole are respectively disposed on common line and in contact with an extending portion of the first thin film transistor and an extending portion of the second thin film transistor. A dummy line is disposed at a side of the data line, and a third via hole is disposed both on the dummy line and on the common line. The present invention can not only increase the aperture ratio of the pixel, but have a better stability of the common voltage signal.

Abstract: A thin film transistor structure of a pixel is provided. In the present invention, a first metal layer serves as a gate electrode, and the gate electrode includes an extending gate electrode portion. A second metal layer includes a drain electrode partially and respectively overlapping the gate electrode and the gate electrode portion with the amorphous silicon layer interposed therebetween so as to form a first parasitic capacitor and a second parasitic capacitor. The total capacitance of the first parasitic capacitor and the second parasitic capacitor is invariable to withstand deviation caused by vibration of the machine in the photolithographic process, so that undesired effects in the liquid crystal display panel such as mura and flicker can be reduced.

Abstract: Disclosed is a pixel layout structure capable of increasing the capability of detecting amorphous silicon (a-Si) residue defects and a method for manufacturing the same. Wherein, an a-Si dummy layer is disposed on either one side or both sides of each data line. The design of such an a-Si dummy layer is utilized, so that in an existing testing conditions (by making use of an existing automatic array tester in carrying out the test), in case that there exists an a-Si residue in a pixel, the pixel having defects can be detected through an enhanced capacitance coupling effect and an electron conduction effect. Therefore, through the application of the above-mentioned design, the capability of an automatic array tester can effectively be increased in detecting a defective pixel having a-Si residues.

Abstract: A pixel structure includes a scan line, a data line, a gate electrode electrically connected to the scan line, a semiconductor layer disposed on the gate electrode, a drain electrode, an extending electrode, and a pixel electrode. The scan line and the data line cross each other, and are insulated. The drain electrode includes a contact part disposed outside the gate electrode, an electrode part disposed on the semiconductor pattern and a connecting part extending from the contact part along a direction to connect the electrode part, and partially overlapping the gate electrode. The pixel electrode is connected to the contact part. The extending electrode is connected to the scan line. A first end of the extending electrode points to the semiconductor layer along the direction, and overlaps the drain electrode. A first width of the connecting part is equal to the second width of the extending electrode.

Abstract: A touch panel disposed on a display panel includes a substrate, a plurality of first sensing strings and second sensing strings, and a plurality of assistant lines. The first sensing strings and the second sensing strings include sensing pads, a plurality of first connecting lines and a plurality of second connecting lines. The first connecting lines are parallel to a first direction and electrically connected to portions of the sensing pads in series to construct the first sensing strings. The second connecting lines are parallel to a second direction and electrically connected to the other portions of the sensing pads in series to construct the second sensing strings. The first and the second sensing pads are coplanar. The first connecting lines are electrically insulated from the second connecting lines. The assistant lines are positioned within an area of the sensing pads. The assistant lines directly contact with the sensing pads.

Abstract: A pixel array includes scan lines extended along a row direction in a zigzag manner, data lines extended along a column direction, and pixels connected the scan lines and the data lines. Each pixel arranged in nth row includes a first sub-pixel and a second sub-pixel. The first sub-pixel includes a first transistor and a first pixel electrode. A first gate electrode and a first drain electrode of the first transistor are respectively connected to the (n+1)th scan line and the first pixel electrode. A second sub-pixel includes a second transistor and a second pixel electrode. A second gate electrode and a second drain electrode of the second transistor are respectively connected to the nth scan line and the second sub-pixel electrode. A first source electrode of the first transistor and a second source electrode of the second transistor are connected to the same data line.

Abstract: A pixel structure includes a scan line, a data line, a gate electrode, a semiconductor layer, a source electrode, a drain electrode including a comb-shaped part surrounding the source electrode and a connecting part, and a pixel electrode electrically connected to the drain electrode. The scan line and the data line are arranged intersectedly and electrically insulated from each other. At least a portion of the source electrode and the drain electrode are disposed on the semiconductor layer. At least one branch of the comb-shaped part extends outside one side of the gate electrode to form a protrusion part. The connecting part extends from the comb-shaped part beyond the other side of the gate electrode. The protrusion part and the connecting part aligned with the margin of the gate electrode have a first width and a third width respectively, wherein the first width substantially equals to the third width.