Abstract: A system and method for symmetrical filtering of an input string may include loading, into at least one vector register, in a single read cycle, a subset of right-side data elements and a subset of left-side data elements of the input string. The input string may be stored sequentially in a memory unit. The right-side data elements and the left-side data elements may be equally distant from the center of the input string and may be separated by a whole number of rows in the memory. The system and method may include performing filtering of the input string using a symmetrical filter with the loaded right-side data elements and left-side data elements.

Abstract: A system and method is provided for executing a conditional branch instruction. The system and method may include a branch predictor to predict one or more instructions that depend on the conditional branch instruction and a branch mis-prediction buffer to store correct instructions that were not predicted by the branch predictor during a branch mis-prediction.

Abstract: Device and method for writing Discrete Fourier transform (DFT) samples in a memory in a reorder stage, the memory includes memory banks, each having a dedicated address generator. The method includes: dividing the DFT samples into R(reorder) equally sized segments, where R(reorder) is the radix value of the reorder stage of the DFT; checking whether a number of butterfly computations per cycle of a reorder stage of the DFT operation times R(reorder), denoted as P, is not larger than the number of segments; if P is larger than the number of segments: further dividing the segments or sub-segments into X equally sized sub-segments, where X is a radix value of a next stage of the DFT operation until P is not larger than the number of sub-segments; and mapping the sub-segments to the memory, each in a separate row, with an offset that includes segment offset and sub-segment offset.

Abstract: A method and system for soft output multiple-input-multiple-output (MIMO) decoding may include generating a tree-graph based on: MIMO rank, number of bits per layer, and type of modulation, wherein the tree-graph comprises a root node, leaf nodes, nodes, and branches connecting the nodes; performing sphere decoding by determining a radius covering a subset of nodes within said tree-graph; managing, based on the sphere decoding, tables comprising metrics and counter metrics usable for log likelihood ratio (LLR) generation; predicting, based on a specified prediction scheme, counter metrics for paths in the tree-graph that comprise nodes and branches out of the determined radius; and updating the tables comprising the counter metrics with the predicted counter metric, in a case that the predicted counter metrics are better in maximum likelihood terms than the determined counter metrics.

Abstract: A decoder to search a tree graph to decode a received signal. The tree graph may have a plurality of levels, each level having a plurality of nodes and each node representing a different value of an element of a candidate transmit signal corresponding to the received signal. The decoder may include a first module to execute a branch prediction at each branch node to select one of a plurality of candidate nodes stemming from the branch node that has a smallest distance increment, and a second module, running in parallel to the first module, to evaluate the branch prediction made by the first module at each branch node by computing an accumulated distance of the selected node. If the accumulated distance of the selected node is greater than or equal to a search radius, the first module may override the branch prediction and select an alternative candidate node.

Abstract: A decoder to search a tree graph to decode a received signal y. The tree graph may have a plurality of levels, each level having a plurality of nodes and each node representing a different value of an element of a candidate transmit signal s corresponding to the received signal y. The decoder may include a first module to execute a branch prediction at each branch node of the tree graph to select one of a plurality of candidate nodes stemming from the branch node that has a smallest distance increment. The decoder may include a second module, running in parallel to the first module, to evaluate the branch prediction made by the first module at each branch node by computing an accumulated distance of the selected node. If the accumulated distance of the selected node is greater than or equal to a search radius, the first module may override the branch prediction and select an alternative candidate node.

Abstract: A system and method for locking data in a cache memory. A first processing thread may be operated to run a program requesting data, where at least some of the requested data is loaded from a source memory into a non-empty cache. A second processing thread may be operated independently of the first processing thread to determine whether or not to lock the requested data in the cache. If the requested data is determined to be locked, the requested data may be locked in the cache at the same time as the data is loaded into the cache.

Abstract: A device system and method for processing program instructions, for example, to execute intra vector operations. A fetch unit may receive a program instruction defining different operations on data elements stored at the same vector memory address. A processor may include different types of execution units each executing a different one of a predetermined plurality of elemental instructions. Each program instruction may be a combination of one or more of the elemental instructions. The processor may receive a vector of data elements stored non-consecutively at the same vector memory address to be processed by a same one of the elemental instructions and a vector of configuration values independently associated with executing the same elemental instruction on the non-consecutive data elements. At least two configuration values may be different to implement different operations by executing the same elemental instruction using the different configuration values on the vector of non-consecutive data elements.

Abstract: Embodiments of the invention are directed to system and method that enable relatively low power dissipation by scheduling operations of multiply accumulators chain of two or more multiply accumulators units by delivering an output result of a first multiply accumulator of the chain as an input to a second subsequent multiply accumulator of the chain.

Abstract: A system, processor, and method are provided for encoding a data block, for example, of digital data. A processor may, from among a plurality of intra frame encoding modes each having a different direction for extrapolating already encoded pixels adjacent to the block, select an intra coding mode having a direction that most closely matches a direction of minimum pixel value change of the block. The processor may compute a predicted intra frame encoding residual data for the block associated with the selected mode based on the difference between the direction of the selected intra frame encoding mode and the direction of minimum pixel value change of the block. The processor may compute inter frame encoding residual data and compare the intra and inter frame encoding residual data. The processor may compress the data block using the intra or inter frame encoding having the smaller residual data.

Abstract: A system and method of data transfer that collapses a multi-dimensional data array while preserving neighboring connectivity. One or more program instructions may be received that request input data comprising a sub-set of data elements from a first data array in an external memory. The sub-set of data elements may be transferred from the first data array in the external memory to a second data array in an internal memory. The retrieved sub-set of requested data elements may be stored in the second array in respective positions translated from the positions in the first array by a plurality of omitted rows and columns from the first data array from which no data elements are requested.

Abstract: A system, processor and method are provided for digital signal processing. A processor may initiate processing a sequence of instructions followed by an interrupt. Each instruction may be processed in respective sequential pipeline slots. A branch detector may detect or determine if an instruction is a branch instruction, for example, in turn, for each sequential instruction. In one embodiment, the branch detector may detect if an instruction is a branch instruction until at least a first branch instruction is detected. A processor may annul instructions which are determined to be branch instructions when the interrupt occupies a delay slot associated with the branch instruction. An execution unit may execute at least the sequence of instructions to run a program. The branch detector and/or execution unit may be integral or separate from each other and from the processor.

Abstract: Embodiments of the invention are directed to a system and method for sub-pixel motion estimation for video encoding. The method includes providing a best match between a source frame and a reference frame by generating a plurality of non linear building surfaces, generating, in real time, an estimated matching criteria surface representing a matching criteria between the source frame and the reference frame based on the building surfaces and a plurality of sample points of an actual matching criteria surface and selecting, in real time, a position on the estimated matching criteria surface.

Abstract: A system, processor, and method for processing multiple dimension data. A single rectangular data array having a single data port may store a set of data elements representing a multi-dimensional pixel array. A load/store unit may receive the set of data elements and store them divided among a plurality of individually addressable data arrays each having separate address ports. Each individually addressable data array may include at most a single row that stores data elements from a sub-set of the set of data elements representing a multi-dimensional sub-array of the pixel array. A processor may simultaneously access the single row of each of the plurality of individually addressable data arrays by accessing the corresponding respective address ports for each individually addressable data array to retrieve the complete sub-set of data elements in a single computational cycle. An execution unit may execute instruction(s) on the sub-set of data elements.

Abstract: A system and method for controlling video compression quantization comprising generating a quantizer scale offset based on diagonal frequencies of luminance components of a data block samples, luminance intensity of the samples and motion activity of the data block, adjusting a first quantizer scale using the quantizer scale offset to receive a second quantizer scale and quantizing the data block using the second quantizer scale.

Abstract: A method and system for transferring data in a multi ordered memory array from a source memory array to a destination memory array, at least one of which is multi-ordered. A reading memory access unit reads data from the source memory array according to a source access template and a writing memory access unit writes the data to the destination memory array according to a destination access template.

Abstract: A processor core architecture includes a cluster having at least a register file and predefined functional units having access to the register file. The architecture also includes an interface to one or more arbitrary functional units external to the processor core. The interface is to provide the arbitrary functional units with access to the register file.

Abstract: A method for the generation of addresses of successive pairs of input data values of stages of a Fast Fourier Transform calculation stored contiguously in a memory includes initializing at most once per stage a first base address pointer to an address of a first input data value of an initial butterfly calculation of the stage and a second base address pointer to an address of a second input data value of the initial butterfly calculation, and initializing at most once per stage a first constant and a second constant. Pairs of input data values of successive butterfly calculations in the stage are then addressed using the first base address pointer, the second base address pointer, the first constant and the second constant.

Abstract: A system having at least one breakpoint generating module and a core processor and method for providing mutual breakpoint capabilities to at least one breakpoint generating module and a core processor in a computing device. Each breakpoint generating module is capable of generating a first breakpoint message for allowing operation of the core processor and each breakpoint generating module to be halted. A second breakpoint message allows operation of the core processor to be halted. The second breakpoint message corresponds to the first breakpoint message. In addition, the core processor generates a third breakpoint message for allowing operation of the core processor and each breakpoint generating module to be halted.

Abstract: A system having at least one breakpoint generating module and a core processor and method for providing mutual breakpoint capabilities to at least one breakpoint generating module and a core processor in a computing device. Each breakpoint generating module is capable of generating a first breakpoint message for allowing operation of the core processor and each breakpoint generating module to be halted. A second breakpoint message allows operation of the core processor to be halted. The second breakpoint message corresponds to the first breakpoint message. In addition, the core processor generates a third breakpoint message for allowing operation of the core processor and each breakpoint generating module to be halted.