Abstract: The present disclosure relates to the technical field of semiconductor manufacturing, and provides a semiconductor structure and a forming method thereof. The forming method includes: providing a semiconductor substrate, where a surface of the semiconductor substrate is provided with a plurality of conductive structures arranged at intervals; forming sidewall dielectric layers on surfaces of the conductive structures, and then depositing sequentially and alternately to form at least two supporting layers and sacrificial layers; etching the supporting layers and the sacrificial layers to form contact holes exposing the surfaces of the conductive structures; and forming an electrode layer on surfaces of the contact holes.

Abstract: The present disclosure relates to the field of semiconductor technologies, and provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a semiconductor base, bit lines and word lines, wherein a plurality of active regions is provided in the semiconductor base; the bit lines are disposed in the semiconductor base, extend in a first direction and are connected to the active regions; and the word lines are disposed on the semiconductor base above the bit lines, extend in a second direction, and intersect with the active regions.

Abstract: Some embodiments of the present application provide a photomask and its manufacturing method. The photomask includes: a substrate and a light shielding layer located on the substrate, an opening for exposing a surface of the substrate being formed in the light shielding layer; a barrier layer, the barrier layer covering a side wall of the opening and having its bottom contacted with the substrate.

Abstract: The present disclosure relates to the technical field of semiconductor manufacturing, and provides a semiconductor structure and a forming method thereof. The forming method includes: providing a semiconductor substrate, where a surface of the semiconductor substrate is provided with a plurality of conductive structures arranged at intervals; etching a surface of the conductive structure into a curved surface, and then depositing sequentially to form a first protective layer, a second protective layer and a third protective layer; etching the first protective layer, the second protective layer and the third protective layer to form a contact hole exposing the etched curved surface of the conductive structure; and forming a mask layer on a surface of the contact hole.

Abstract: A method and an apparatus for testing an adjustment circuit is applied to a test platform. The adjustment circuit includes a duty cycle adjuster (DCA) circuit. The method includes: receiving written data at a specified storage address based on a first read/write clock signal; and receiving read data from the specified storage address based on a second read/write clock signal, and generating a test result of the DCA circuit based on the written data and the read data; wherein the DCA circuit is configured to adjust a first initial read/write clock signal to generate the first read/write clock signal and/or adjust a second initial read/write clock signal to generate the second read/write clock signal, and a duty cycle of the first initial read/write clock signal and/or a duty cycle of the second initial read/write clock signal have/has a first deviation.

Abstract: The present disclosure provides a manufacturing method for semiconductor structure and a semiconductor structure. The manufacturing method includes: providing a substrate; forming first mask patterns and first mask openings on the substrate, the first mask opening being located between the adjacent first mask patterns; forming second mask patterns and second mask openings on the first mask patterns and the first mask openings, the second mask opening being located between the adjacent second mask patterns; and forming first patterns and first openings on the substrate based on the first mask patterns, the first mask openings, the second mask patterns and the second mask openings.

Abstract: A current test circuit can include a sampling resister array with a control end connected with a main control component, a first end is connected with a power conversion circuit, and a second end configured to be connected with a component to be tested. The sampling resistor array includes at least two sampling branches, each having an analog switch and a sampling resistor connected serially. In the test, the main control component can generate a control signal according to the operating state of the component and gate at least one sampling branch of the sampling resistor array through the control signal, obtain voltage values at two ends of the sampling resistor array through a voltage test assembly, and determine the current of the component according to the voltage values at two ends of the sampling resistor array and resistance values of the sampling resistor array.

Abstract: A sense amplifier circuit includes: a charge module configured to charge a set signal node and a reset signal node according to a clock signal; and a sense module configured to sense and amplify a differential input signal according to the clock signal; where, the sense module includes a first amplification circuit, a second amplification circuit, and a cross hopping transfer circuit cross-connected between the first amplification circuit and the second amplification circuit. The cross hopping transfer circuit is configured to transfer a valid signal of a newly started amplification circuit to another amplification circuit if sensing is completed and the differential input signal hops, such that a set signal/reset signal remains unchanged. A flip-flop includes the sense amplifier circuit.

Abstract: The present disclosure discloses a capacitor structure and its formation method and a memory. The method includes: providing a substrate; forming an electrode support structure on the substrate in a stacking fashion, wherein the electrode support structure includes at least a first support layer on its top, a capacitor hole is formed at intervals within the electrode support structure and extends upwards in a direction perpendicular to a surface of the substrate; forming, within the capacitor hole, an electrode post and an electrode layer extending from the electrode post to the upper surface of the first support layer; removing the electrode layer; removing the first support layer; forming a dielectric layer on the top of the electrode support structure, wherein the dielectric layer covers the top of the electrode post, and an outer peripheral wall of the top of the electrode post is connected with the dielectric layer.

Abstract: A method for forming the packaging structure includes: providing a substrate; forming a plurality of mutually independent conductive wires on the substrate, wherein a trench is provided between adjacent conductive wires; oxidizing side walls of each of the conductive wires to form a barrier layer; and forming a solder mask at least filling the trench.

Abstract: A method and apparatus for testing a command are provided. The method includes that: when the test platform exists a target command to be sent to a memory, a duration of a deselect command is determined according to a minimum time interval between a target command and each of historical commands and the time when the each of the historical commands is sent and the present time; the target command is sent to the memory after the deselect command.

Abstract: Embodiments of the present application provide a method for processing a semiconductor structure and a method for forming a semiconductor structure. The method for processing a semiconductor structure includes: providing a semiconductor substrate, the semiconductor substrate being provided with a feature portion, the aspect ratio of the feature portion being greater than a preset aspect ratio, a mask layer being provided on the top of the feature portion; ashing a semiconductor structure, the semiconductor structure comprising the semiconductor substrate, the feature portion, and the mask layer; cleaning the semiconductor structure; drying the semiconductor structure; and removing the mask layer.

Abstract: The present disclosure provides a comparator and a decision feedback equalization circuit. The comparator includes: a first sampling circuit provided with an output terminal, and configured to generate, under the control of a first control signal and a clock signal, a first differential signal according to a signal to be compared and a first reference signal; a second sampling circuit provided with an output terminal connected to the output terminal of the first sampling circuit, and configured to generate, under the control of a second control signal and the clock signal, a second differential signal according to the signal to be compared and a second reference signal, where the first reference signal is larger than the second reference signal.

Abstract: A method for determining a sense boundary of a sense amplifier includes: writing the same data into the memory cells controlled by at least a pair of first word line on the left side and second word line on the right side corresponding to the sense amplifier; activating the first word line and precharging bit lines corresponding to the first word line; reading the data in the memory cells controlled by the corresponding second word line after a preset row precharge time; and determining a corresponding critical row precharge time as a row precharge time boundary value when the sense amplifier does not correctly read the data in the memory cells controlled by the second word line.

Abstract: The present disclosure relates to a method and apparatus for determining a signal margin (SM) of a memory cell, a storage medium and an electronic device, and relates to the technical field of integrated circuits. The method for determining an SM of a memory cell includes: when the memory cell performs write and read operations, determining a sense signal threshold of the memory cell under an influence of a noise; and determining, based on the sense signal threshold, an actual SM of the memory cell during data reading.

Abstract: An input sampling method includes the following operations. A first pulse signal and a second pulse signal are received. Logical operation is performed on the first pulse signal and the second pulse signal to determine a to-be-sampled signal. The to-be-sampled signal is obtained by shielding an invalid part of the second pulse signal according to a logical operation result. Sampling process is performed on the to-be-sampled signal to obtain a target sampled signal.

Abstract: Some examples of the present disclosure provide a method for manufacturing a wire layer. The method for manufacturing a wire layer includes steps in which a wafer having an opening is provided; conductive grains are deposited on the wafer, and on a bottom and a side wall of the opening to form a conductive film, during which a temperature of a surface of the wafer is lower than a flowing temperature of the conductive film, and when the temperature of the surface of the wafer is greater than or equal to the flowing temperature, the conductive film starting to flow; and after the conductive film is formed, the temperature of the surface of the wafer is elevated to perform a reflowing process, such that the conductive film is converted to a conductive layer filling up the opening.

Abstract: Provided is a drive circuit, including drive units, a pre-drive module, and a resistance value selection circuit. Pull-up resistors of the drive units are adjustable; the pre-drive module is connected to M drive units and controls the pull-up resistors of the M drive units and resistance values of the pull-up resistors through a drive control signal, the M being an integer greater than 1; the resistance value selection circuit is connected to the pre-drive module and configured to select one of a first code and a second code for outputting as a target code according to a selection signal; and the pre-drive module outputs the drive control signal according to the target code.

Abstract: A base die is configured to: receive first data in a writing phase, perform error correction code encoding processing to generate encoded data, and transmit second data to a memory die in the writing phase, wherein the second data includes the first data and the encoded data; and receive the second data from the memory die in a reading phase, perform error checking and correction processing, and transmit third data in the reading phase, wherein the third data is the first data after the error checking and correction processing.

Abstract: The present disclosure provides a chip test method, apparatus, and a device, and a storage medium. The chip test method includes: determining a register test adaptation file based on a register description file under a preset test environment, wherein a form of the register test adaptation file matches that of a predetermined test case template; constructing a test case based on the register test adaptation file and the test case template, and executing the test case to test a chip, wherein the determining a register test adaptation file further includes: when the preset test environment changes, determining change information of the register description file in response to the change; and changing the register test adaptation file based on the change information.