Patents Assigned to Chaologix, Inc.
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Patent number: 11526646Abstract: A power planning phase module, a placement phase module, and a routing phase module are provided that can replace, supplement, or enhance existing electronic design automation (EDA) software tools. The power planning phase module adds distributed power sources and a network of switching elements to the power frame or ring assigned to regions of a chip (that may be identified during a floor planning stage). The placement phase module optimizes a number and type of cells attached to each power source of the distributed power sources already added or to be added during the power planning phase. The routing phase module optimizes routing length to, for example, mask power consumption.Type: GrantFiled: November 13, 2020Date of Patent: December 13, 2022Assignee: CHAOLOGIX, INC.Inventors: Subbayya Chowdary Yanamadala, Daniel F. Yannette, Brent Arnold Myers
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Patent number: 10860771Abstract: A power planning phase module, a placement phase module, and a routing phase module are provided that can replace, supplement, or enhance existing electronic design automation (EDA) software tools. The power planning phase module adds distributed power sources and a network of switching elements to the power frame or ring assigned to regions of a chip (that may be identified during a floor planning stage). The placement phase module optimizes a number and type of cells attached to each power source of the distributed power sources already added or to be added during the power planning phase. The routing phase module optimizes routing length to, for example, mask power consumption.Type: GrantFiled: February 7, 2017Date of Patent: December 8, 2020Assignee: CHAOLOGIX, INC.Inventors: Subbayya Chowdary Yanamadala, Daniel F. Yannette, Brent Arnold Myers
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Patent number: 10756710Abstract: A clock generator includes a series of inverting stages; and at least one combinational logic stage. The series of inverting stages is tapped at two or more locations along the series of inverting stages to provide intermediary outputs. A combinational logic stage of the at least one combinational logic stage is coupled to receive two or more of the intermediary outputs and generate a clock signal. Multi-phase, multi-duty cycle, non-overlapping clock signals can be generated by the clock generator based on different combinations of intermediary outputs. The clock signals can be provided to a switching network.Type: GrantFiled: April 11, 2018Date of Patent: August 25, 2020Assignee: CHAOLOGIX, INC.Inventors: Timothy Arthur Bell, Daniel F. Yannette
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Patent number: 10419019Abstract: A data compression system can include a compression unit comprising a single chaotic system having an identified initial condition that produces a desired output sequence of data corresponding to a data set being stored. The single chaotic system can be identified using a chain of controlled nonlinear systems and a dynamical search technique to match the output, in sequence over consecutive time intervals with the chain of the controlled nonlinear systems.Type: GrantFiled: November 13, 2016Date of Patent: September 17, 2019Assignee: CHAOLOGIX, INC.Inventor: Abraham Miliotis
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Patent number: 10263620Abstract: A floating core network for secure isolation of a circuit from an external supply interface is described. Isolation of a core is accomplished through a dynamic current limiting network providing an isolated core voltage to the core; and an isolated supply for the corresponding core that is continuously recharged by the dynamic current limiting network. The dynamic current limiting network can include two control loops, one control loop providing a fixed gate voltage to a p-type transistor supplying current to the isolated supply and another control loop providing a fixed gate voltage to an n-type transistor sinking current from the isolated supply.Type: GrantFiled: December 1, 2017Date of Patent: April 16, 2019Assignee: CHAOLOGIX, INC.Inventors: Timothy Arthur Bell, Brent Arnold Myers
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Patent number: 9853640Abstract: A floating core network for secure isolation of a circuit from an external supply interface is described. Isolation of a core is accomplished through a dynamic current limiting network providing an isolated core voltage to the core; and an isolated supply for the corresponding core that is continuously recharged by the dynamic current limiting network. The dynamic current limiting network can include two control loops, one control loop providing a fixed gate voltage to a p-type transistor supplying current to the isolated supply and another control loop providing a fixed gate voltage to an n-type transistor sinking current from the isolated supply.Type: GrantFiled: July 7, 2015Date of Patent: December 26, 2017Assignee: Chaologix, Inc.Inventors: Timothy Arthur Bell, Brent Arnold Myers
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Patent number: 9430678Abstract: Advantageous analog and/or digital logic cells and methods of powering circuit blocks using the same are provided. A digital logic cell can include a charge storage device, a logic block, and connections to a power supply. The charge storage device may be a capacitor. The capacitor or other charge storage device can be disconnected from the logic block and a power supply to discharge the capacitor, and then connected to the power supply, via the power supply connections, to charge the capacitor. The capacitor can be disconnected from a ground connection of the power supply while the capacitor is discharged. After being charged via the power supply, the capacitor can also be disconnected from the power supply (including ground) and connected to the logic block to power the logic block.Type: GrantFiled: September 9, 2015Date of Patent: August 30, 2016Assignee: CHAOLOGIX, INC.Inventors: Daniel F. Yannette, Brent Arnold Myers
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Patent number: 9312861Abstract: Disclosed is a novel circuit able to generate any logic combination possible as a function of the input logic signals. The circuit is described as a 2 input logistic map circuit but may be expanded to 3 or more inputs as required. Further disclosed is a universal logic array with variable circuit topology. A metallization layer and/or a via interconnection between cells in the array elements produce a circuit topology that implements a Boolean function and/or chaotic function and/or a logic function. The novel circuit provides a circuit topology for secure applications with no obvious physical correspondence between control signal values and input to output mapping. Further disclosed is a network which has a power signature independent of input signal state and output transition. This provides a very useful circuit to protect data from decryption from power signature analysis in secure applications.Type: GrantFiled: September 30, 2014Date of Patent: April 12, 2016Assignee: CHAOLOGIX, INC.Inventors: Brent Arnold Myers, James Gregory Fox
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Patent number: 9154132Abstract: Advantageous analog and/or digital logic cells and methods of powering circuit blocks using the same are provided. A digital logic cell can include a charge storage device, a logic block, and connections to a power supply. The charge storage device may be a capacitor. The capacitor or other charge storage device can be disconnected from the logic block and a power supply to discharge the capacitor, and then connected to the power supply, via the power supply connections, to charge the capacitor. The capacitor can be disconnected from a ground connection of the power supply while the capacitor is discharged. After being charged via the power supply, the capacitor can also be disconnected from the power supply (including ground) and connected to the logic block to power the logic block.Type: GrantFiled: November 7, 2014Date of Patent: October 6, 2015Assignee: CHAOLOGIX, INC.Inventors: Daniel F. Yannette, Brent Arnold Myers
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Patent number: 8912814Abstract: Advantageous digital logic cells and methods of powering logic blocks using the same are provided. A digital logic cell can include a charge storage device, a logic block, and connections to a power supply. The charge storage device may be a capacitor. The capacitor or other charge storage device can be disconnected from the logic block and a power supply to discharge the capacitor, and then connected to the power supply, via the power supply connections, to charge the capacitor. The capacitor can be disconnected from a ground connection of the power supply while the capacitor is discharged. After being charged via the power supply, the capacitor can also be disconnected from the power supply (including ground) and connected to the logic block to power the logic block.Type: GrantFiled: May 31, 2013Date of Patent: December 16, 2014Assignee: Chaologix, Inc.Inventors: Daniel F. Yannette, Brent Arnold Myers
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Patent number: 8912816Abstract: Advantageous analog and/or digital logic cells and methods of powering circuit blocks using the same are provided. A digital logic cell can include a charge storage device, a logic block, and connections to a power supply. The charge storage device may be a capacitor. The capacitor or other charge storage device can be disconnected from the logic block and a power supply to discharge the capacitor, and then connected to the power supply, via the power supply connections, to charge the capacitor. The capacitor can be disconnected from a ground connection of the power supply while the capacitor is discharged. After being charged via the power supply, the capacitor can also be disconnected from the power supply (including ground) and connected to the logic block to power the logic block.Type: GrantFiled: February 19, 2014Date of Patent: December 16, 2014Assignee: Chaologix, Inc.Inventors: Daniel F. Yannette, Brent Arnold Myers
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Patent number: 8860465Abstract: Disclosed is a novel circuit able to generate any logic combination possible as a function of the input logic signals. The circuit is described as a 2 input logistic map circuit but may be expanded to 3 or more inputs as required. Further disclosed is a universal logic array with variable circuit topology. A metallization layer and/or a via interconnection between cells in the array elements produce a circuit topology that implements a Boolean function and/or chaotic function and/or a logic function. The novel circuit provides a circuit topology for secure applications with no obvious physical correspondence between control signal values and input to output mapping. Further disclosed is a network which has a power signature independent of input signal state and output transition. This provides a very useful circuit to protect data from decryption from power signature analysis in secure applications.Type: GrantFiled: November 9, 2012Date of Patent: October 14, 2014Assignee: Chaologix, Inc.Inventors: Brent Arnold Myers, James Gregory Fox
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Publication number: 20140167837Abstract: Advantageous analog and/or digital logic cells and methods of powering circuit blocks using the same are provided. A digital logic cell can include a charge storage device, a logic block, and connections to a power supply. The charge storage device may be a capacitor. The capacitor or other charge storage device can be disconnected from the logic block and a power supply to discharge the capacitor, and then connected to the power supply, via the power supply connections, to charge the capacitor. The capacitor can be disconnected from a ground connection of the power supply while the capacitor is discharged. After being charged via the power supply, the capacitor can also be disconnected from the power supply (including ground) and connected to the logic block to power the logic block.Type: ApplicationFiled: February 19, 2014Publication date: June 19, 2014Applicant: Chaologix, Inc.Inventors: DANIEL F. YANNETTE, BRENT ARNOLD MYERS
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Publication number: 20140132337Abstract: Advantageous digital logic cells and methods of powering logic blocks using the same are provided. A digital logic cell can include a charge storage device, a logic block, and connections to a power supply. The charge storage device may be a capacitor. The capacitor or other charge storage device can be disconnected from the logic block and a power supply to discharge the capacitor, and then connected to the power supply, via the power supply connections, to charge the capacitor. The capacitor can be disconnected from a ground connection of the power supply while the capacitor is discharged. After being charged via the power supply, the capacitor can also be disconnected from the power supply (including ground) and connected to the logic block to power the logic block.Type: ApplicationFiled: May 31, 2013Publication date: May 15, 2014Applicant: CHAOLOGIX, INC.Inventors: DANIEL F. YANNETTE, BRENT ARNOLD MYERS
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Publication number: 20130063179Abstract: Disclosed is a novel circuit able to generate any logic combination possible as a function of the input logic signals. The circuit is described as a 2 input logistic map circuit but may be expanded to 3 or more inputs as required. Further disclosed is a universal logic array with variable circuit topology. A metallization layer and/or a via interconnection between cells in the array elements produce a circuit topology that implements a Boolean function and/or chaotic function and/or a logic function. The novel circuit provides a circuit topology for secure applications with no obvious physical correspondence between control signal values and input to output mapping. Further disclosed is a network which has a power signature independent of input signal state and output transition. This provides a very useful circuit to protect data from decryption from power signature analysis in secure applications.Type: ApplicationFiled: November 9, 2012Publication date: March 14, 2013Applicant: CHAOLOGIX, INC.Inventors: BRENT ARNOLD MYERS, JAMES GREGORY FOX
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Patent number: 8330493Abstract: Disclosed is a novel circuit able to generate any logic combination possible as a function of the input logic signals. The circuit is described as a 2 input logistic map circuit but may be expanded to 3 or more inputs as required. Further disclosed is a universal logic array with variable circuit topology. A metallization layer and/or a via interconnection between cells in the array elements produce a circuit topology that implements a Boolean function and/or chaotic function and/or a logic function. The novel circuit provides a circuit topology for secure applications with no obvious physical correspondence between control signal values and input to output mapping. Further disclosed is a network which has a power signature independent of input signal state and output transition. This provides a very useful circuit to protect data from decryption from power signature analysis in secure applications.Type: GrantFiled: October 13, 2010Date of Patent: December 11, 2012Assignee: Chaologix, Inc.Inventors: Brent A. Myers, James G. Fox
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Publication number: 20110085662Abstract: Disclosed is a novel circuit able to generate any logic combination possible as a function of the input logic signals. The circuit is described as a 2 input logistic map circuit but may be expanded to 3 or more inputs as required. Further disclosed is a universal logic array with variable circuit topology. A metallization layer and/or a via interconnection between cells in the array elements produce a circuit topology that implements a Boolean function and/or chaotic function and/or a logic function. The novel circuit provides a circuit topology for secure applications with no obvious physical correspondence between control signal values and input to output mapping. Further disclosed is a network which has a power signature independent of input signal state and output transition. This provides a very useful circuit to protect data from decryption from power signature analysis in secure applications.Type: ApplicationFiled: October 13, 2010Publication date: April 14, 2011Applicant: Chaologix, Inc.Inventors: Brent A. MYERS, James G. Fox
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Patent number: 7925814Abstract: A dynamically configurable logic gate includes an input summer for receiving a first input signal and a second input signal to generate a summed input signal. Further the dynamically configurable logic gate includes a nonlinear element that applies a nonlinear function to the summed input signal to produce a nonlinear output signal. The dynamically configurable logic gate output signal corresponds to one of a plurality of different logic gates responsive to adjusting the summed input signal and/or the nonlinear function. In another embodiment, the dynamically configurable logic gate includes feedback to one of the inputs. The dynamically configurable logic gate receives the two inputs and operates as one of a plurality of different logic gate types so as to produce an output signal that corresponds to a memory latch according to a selection of the control signal. An array structure of dynamically configurable logic elements is also disclosed.Type: GrantFiled: May 8, 2008Date of Patent: April 12, 2011Assignee: Chaologix, Inc.Inventor: Robert A. Schneiderwind
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Publication number: 20110006807Abstract: A dynamically configurable logic gate includes an input summer for receiving a first input signal and a second input signal to generate a summed input signal. Further the dynamically configurable logic gate includes a nonlinear element that applies a nonlinear function to the summed input signal to produce a nonlinear output signal. The dynamically configurable logic gate output signal corresponds to one of a plurality of different logic gates responsive to adjusting the summed input signal and/or the nonlinear function. In another embodiment, the dynamically configurable logic gate includes feedback to one of the inputs. The dynamically configurable logic gate receives the two inputs and operates as one of a plurality of different logic gate types so as to produce an output signal that corresponds to a memory latch according to a selection of the control signal. An array structure of dynamically configurable logic elements is also disclosed.Type: ApplicationFiled: May 8, 2008Publication date: January 13, 2011Applicant: Chaologix, Inc.Inventor: Robert A. Schneiderwind
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Patent number: 7453285Abstract: A dynamically configurable logic gate includes an input summer for receiving a first input signal and a second input signal to generate a summed input signal. Further the dynamically configurable logic gate includes a nonlinear element that applies a nonlinear function to the summed input signal to produce a nonlinear output signal. The dynamically configurable logic gate output signal corresponds to one of a plurality of different logic gates responsive to adjusting the summed input signal and/or the nonlinear function. In another embodiment, the dynamically configurable logic gate includes feedback to one of the inputs. The dynamically configurable logic gate receives the two inputs and operates as one of a plurality of different logic gate types so as to produce an output signal that corresponds to a memory latch according to a selection of the control signal. An array structure of dynamically configurable logic elements is also disclosed.Type: GrantFiled: December 22, 2006Date of Patent: November 18, 2008Assignee: Chaologix, Inc.Inventors: Steven Lee Kiel, Douglas Norman Krening, Lark Edward Lehman, Michael Joseph Schneiderwind