Patents Assigned to Chartered Semiconductor Manfacturing Ltd.
  • Integrated circuit with self-aligned line and via and manufacturing method therefor
    Patent number: 7119010
    Abstract: An integrated circuit and manufacturing method therefor is provided having a base with a first dielectric layer formed thereon. A second dielectric layer is formed over the first dielectric layer. A third dielectric layer is formed in spaced-apart strips over the second dielectric layer. A first trench opening is formed through the first and second dielectric layers between the spaced-apart strips of the third dielectric layer. A second trench opening is formed contiguously with the first trench opening through the first dielectric layer between the spaced-apart strips of the third dielectric layer. Conductor metals in the trench openings form self-aligned trench interconnects.
    Type: Grant
    Filed: April 23, 2002
    Date of Patent: October 10, 2006
    Assignee: Chartered Semiconductor Manfacturing Ltd.
    Inventors: Yeow Kheng Lim, Randall Cher Liang Cha, Alex See, Wang Ling Goh
  • Method to create a copper diffusion deterrent interface
    Publication number: 20040227247
    Abstract: Method and product for forming a dual damascene interconnect structure, wherein depositing a copper sulfide interface layer as sidewalls to the opening deters migration or diffusing of copper ions into the dielectric material.
    Type: Application
    Filed: November 21, 2003
    Publication date: November 18, 2004
    Applicant: CHARTERED SEMICONDUCTOR MANFACTURING LTD.
    Inventors: Simon Chooi, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Subbash Gupta, Sudipto Ranendra Roy, Paul Kwok Keung Ho, Yi Xu