Patents Assigned to Chips & Technologies, Inc.
  • Patent number: 9479128
    Abstract: A multi-mode power amplifier comprises a regulation control circuit, an AMP 1, a demultiplexer, an AMP 2, a low power output matching circuit, a medium power output matching circuit, and a high power output matching circuit. In low power mode, the regulation control circuit controls AMP 1 to work in a first power mode, and controls the demultiplexer to couple an output terminal of AMP 1 to the low power output matching circuit. In the medium power mode, the regulation control circuit controls AMP 1 to work in a second power mode, and controls the demultiplexer to couple an output terminal of AMP 1 to the medium power output matching circuit. In high power mode, the regulation control circuit controls AMP 1 to work in the second power mode, and controls the demultiplexer to couple an output terminal of AMP 1 to AMP 2.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: October 25, 2016
    Assignee: CHINA UNI-CHIP TECHNOLOGIES INC.
    Inventor: Kai Xuan
  • Patent number: 9343625
    Abstract: A semiconductor light emitting diode is provided. The semiconductor light emitting diode comprises a metal electrode; an n-type cladding over the metal electrode, the n-type cladding comprising a pillar support part formed of an n-type semiconductor material, and a pillar part having a plurality of pillars formed of an n-type semiconductor material over the pillar support part; an active part conformally formed over the pillar part so as to enclose the pillar part and over the pillar support part between the pillar parts, the active part having a quantum well layer and a barrier layer stacked alternately; a p-type cladding conformally formed of a p-type semiconductor material over the active part; and a transparent electrode formed over the p-type cladding.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: May 17, 2016
    Assignee: Chip Technology Inc.
    Inventors: Byoung gu Cho, Se-Hun Kwon, Jae-Sik Min
  • Publication number: 20150137891
    Abstract: A multi-mode power amplifier comprises a regulation control circuit, an AMP 1, a demultiplexer, an AMP 2, a low power output matching circuit, a medium power output matching circuit, and a high power output matching circuit. In low power mode, the regulation control circuit controls AMP 1 to work in a first power mode, and controls the demultiplexer to couple an output terminal of AMP 1 to the low power output matching circuit. In to medium power mode, the regulation control circuit controls AMP 1 to work in a second power mode, and controls the demultiplexer to couple an output terminal of AMP 1 to the medium power output matching circuit. In high power mode, the regulation control circuit controls AMP 1 to work in the second power mode, and controls the demultiplexer to couple an output terminal of AMP 1 to AMP 2.
    Type: Application
    Filed: August 14, 2014
    Publication date: May 21, 2015
    Applicant: China Uni-Chip Technologies Inc.
    Inventor: Kai Xuan
  • Publication number: 20130168636
    Abstract: A semiconductor light emitting diode is provided. The semiconductor light emitting diode comprises a metal electrode; an n-type cladding over the metal electrode, the n-type cladding comprising a pillar support part formed of an n-type semiconductor material, and a pillar part having a plurality of pillars formed of an n-type semiconductor material over the pillar support part; an active part conformally formed over the pillar part so as to enclose the pillar part and over the pillar support part between the pillar parts, the active part having a quantum well layer and a barrier layer stacked alternately; a p-type cladding conformally formed of a p-type semiconductor material over the active part; and a transparent electrode formed over the p-type cladding.
    Type: Application
    Filed: December 29, 2011
    Publication date: July 4, 2013
    Applicant: CHIP TECHNOLOGY INC.
    Inventors: Byoung gu CHO, Se-Hun Kwon, Jae-Sik Min
  • Publication number: 20110115790
    Abstract: The present inventive concept can be used in a wide range of applications, including: mobile devices, such as mobile phones; an image processing apparatus or processor and computer programs, including a member for converting 2D image signals into 3D image signals or using an algorism for converting 2D image signals into 3D image signals.
    Type: Application
    Filed: August 26, 2008
    Publication date: May 19, 2011
    Applicants: ENHANCED CHIP TECHNOLOGY INC, KWANGWOON UNIVERSITY INDUSTRY-ACADEMIC COLLABORATION FOUNDATION
    Inventors: Ji Sang Yoo, Yun Ki Baek, Se Hwan Park, Jung Hwan Yun, Yong Hyub Oh, Jong Dae Kim, Sung Moon Chun, Tae Sup Jung
  • Patent number: 7797595
    Abstract: Testing of memories that decode a serial stream of address data to access the memory may be performed by either successively halving the number of selected word lines as each address bit is acquired, until a single word line is selected, or by rotating the selection bits in its shift register to select a new set of address lines. As such, a combination of incomplete addressing and rotation can efficiently test large memories by reading and/or writing groups of words. Similar techniques may also be applied to non-memory devices.
    Type: Grant
    Filed: June 18, 2008
    Date of Patent: September 14, 2010
    Assignee: On-Chip Technologies, Inc.
    Inventor: Laurence H. Cooke
  • Publication number: 20100182403
    Abstract: Provided is a file format for encoded image data which can be reproduced into a lifelike stereoscopic image by a display apparatus for displaying a stereoscopic image. The file format for an encoded stereoscopic image includes an image data unit containing image information of the encoded stereoscopic image and a header unit containing meta data used to decode and reproduce the image information of the encoded stereoscopic image contained in the image data unit. The header unit can include at least one header unit of a camera header sub-unit containing information on left and right cameras used to acquire the stereoscopic image, a codec header sub-unit containing information on the encoding of the stereoscopic image, and a display header sub-unit containing information on a barrier type display apparatus for receiving and reproducing the encoded stereoscopic image data.
    Type: Application
    Filed: August 29, 2007
    Publication date: July 22, 2010
    Applicant: ENHANCED CHIP TECHNOLOGY INC.
    Inventors: Sung Moon Chun, Gwang Hoon Park, Doug Young Suh, Kyu Heon Kim, Yong Hyub Oh, Tae Sup Jung
  • Publication number: 20090316506
    Abstract: Testing of memories that decode a serial stream of address data to access the memory may be performed by either successively halving the number of selected word lines as each address bit is acquired, until a single word line is selected, or by rotating the selection bits in its shift register to select a new set of address lines. As such, a combination of incomplete addressing and rotation can efficiently test large memories by reading and/or writing groups of words. Similar techniques may also be applied to non-memory devices.
    Type: Application
    Filed: June 18, 2008
    Publication date: December 24, 2009
    Applicant: ON-CHIP TECHNOLOGIES, INC.
    Inventor: Laurence H. Cooke
  • Patent number: 7353470
    Abstract: Addition of specific test logic may improve the level of test vector compression achieved from existing variable scan test logic. Methods for determining the compressed vectors' states, given the desired uncompressed vectors' values may be used, and techniques for selectively enabling test or other features on a chip by inserting the proper code or codes into the chip may further be used. Techniques may be used to incorporate and apply various types of reset operations to multiple strings of variable scan test logic, as may methods to minimize the test vector compression computation time.
    Type: Grant
    Filed: July 18, 2005
    Date of Patent: April 1, 2008
    Assignee: On-Chip Technologies, Inc.
    Inventors: Laurence H. Cooke, Bulent I. Dervisoglu
  • Publication number: 20070168798
    Abstract: A new technique to determine the placement of exclusive-ors in each scan string of a chip may be used to achieve improved test vector compression, and this may be used along with methods to minimize the overhead of the exclusive-or logic, to eliminate clock enable logic for multiple scan strings, to minimize the changes to existing test logic insertion and scan string reordering, and to minimize the test vector compression computation time.
    Type: Application
    Filed: August 23, 2005
    Publication date: July 19, 2007
    Applicant: On-Chip Technologies, Inc.
    Inventor: Laurence Cooke
  • Publication number: 20070162803
    Abstract: An architecture and methodology for test data compression using combinational functions to provide serial coupling between consecutive segments of a scan-chain are described. Compressed serial-scan sequences are derived starting from scan state identifying desired Care_In values and using symbolic computations iteratively in order to determine the necessary previous scan-chain state until computed previous scan-chain state matches given known starting scan-chain state. A novel design for a new flip-flop is also presented that allows implementing scan-chains that can be easily started and stopped without requiring an additional control signal. Extensions of the architecture and methodology are discussed to handle unknown (X) values in scan-chains, proper clocking of compressed data into multiple scan-chains, the use of a data-spreading network and the use of a pseudo-random signal generator to feed the segmented scan-chains in order to implement Built In Self Test (BIST).
    Type: Application
    Filed: March 1, 2007
    Publication date: July 12, 2007
    Applicant: ON-CHIP TECHNOLOGIES, INC.
    Inventors: Bulent Dervisoglu, Laurence Cooke
  • Patent number: 7234092
    Abstract: A technique to reduce the test data volume and number of scan shift clocks per test pattern by combining the scan inputs with existing values in scan chains and inserting them at additional bit positions along the scan chains in order to reduce the number of shift clocks required to achieve required values at plurality of scan bit positions, and by using multiple taps from the scan chains to form a check-sum in order to reduce the number of scan shift clocks to capture test results.
    Type: Grant
    Filed: January 24, 2003
    Date of Patent: June 19, 2007
    Assignee: On-Chip Technologies, Inc.
    Inventor: Laurence H. Cooke
  • Patent number: 7200784
    Abstract: An architecture and methodology for test data compression using combinational functions to provide serial coupling between consecutive segments of a scan-chain are described. Compressed serial-scan sequences are derived starting from scan state identifying desired Care_In values and using symbolic computations iteratively in order to determine the necessary previous scan-chain state until computed previous scan-chain state matches given known starting scan-chain state. A novel design for a new flip-flop is also presented that allows implementing scan-chains that can be easily started and stopped without requiring an additional control signal. Extensions of the architecture and methodology are discussed to handle unknown (X) values in scan-chains, proper clocking of compressed data into multiple scan-chains, the use of a data-spreading network and the use of a pseudo-random signal generator to feed the segmented scan-chains in order to implement Built In Self Test (BIST).
    Type: Grant
    Filed: September 1, 2004
    Date of Patent: April 3, 2007
    Assignee: On-Chip Technologies, Inc.
    Inventors: Bulent Dervisoglu, Laurence H. Cooke
  • Patent number: 7197681
    Abstract: An architecture and methodology for test data compression using combinational functions to provide serial coupling between consecutive segments of a scan-chain are described. Compressed serial-scan sequences are derived starting from scan state identifying desired Care_In values and using symbolic computations iteratively in order to determine the necessary previous scan-chain state until computed previous scan-chain state matches given known starting scan-chain state. A novel design for a new flip-flop is also presented that allows implementing scan-chains that can be easily started and stopped without requiring an additional control signal. Extensions of the architecture and methodology are discussed to handle unknown (X) values in scan-chains, proper clocking of compressed data into multiple scan-chains, the use of a data-spreading network and the use of a pseudo-random signal generator to feed the segmented scan-chains in order to implement Built In Self Test (BIST).
    Type: Grant
    Filed: January 5, 2004
    Date of Patent: March 27, 2007
    Assignee: On-Chip Technologies, Inc.
    Inventors: Bulent Dervisoglu, Laurence H. Cooke
  • Patent number: 7188286
    Abstract: An architecture and methodology for test data compression using combinational functions to provide serial coupling between consecutive segments of a scan-chain are described. Compressed serial-scan sequences are derived starting from scan state identifying desired Care_In values and using symbolic computations iteratively in order to determine the necessary previous scan-chain state until computed previous scan-chain state matches given known starting scan-chain state. A novel design for a new flip-flop is also presented that allows implementing scan-chains that can be easily started and stopped without requiring an additional control signal. Extensions of the architecture and methodology are discussed to handle unknown (X) values in scan-chains, proper clocking of compressed data into multiple scan-chains, the use of a data-spreading network and the use of a pseudo-random signal generator to feed the segmented scan-chains in order to implement Built In Self Test (BIST).
    Type: Grant
    Filed: September 1, 2004
    Date of Patent: March 6, 2007
    Assignee: On-Chip Technologies, Inc.
    Inventors: Bulent Dervisoglu, Laurence H. Cooke
  • Publication number: 20070050596
    Abstract: A technique for generating a list of all N-bit unsigned binary numbers by starting with an initial number less than some power of 2, successively multiplying the number by that power of 2 and adding the largest non-negative number less than that power of 2 such that the new number is not a duplicate of any of those already generated, and using the resulting lists to generate efficient hashing and serial decoding hardware and software.
    Type: Application
    Filed: August 23, 2005
    Publication date: March 1, 2007
    Applicant: On-Chip Technologies, Inc.
    Inventor: Laurence Cooke
  • Publication number: 20060195746
    Abstract: Addition of specific test logic may improve the level of test vector compression achieved from existing variable scan test logic. Methods for determining the compressed vectors' states, given the desired uncompressed vectors' values may be used, and techniques for selectively enabling test or other features on a chip by inserting the proper code or codes into the chip may further be used. Techniques may be used to incorporate and apply various types of reset operations to multiple strings of variable scan test logic, as may methods to minimize the test vector compression computation time.
    Type: Application
    Filed: July 18, 2005
    Publication date: August 31, 2006
    Applicant: On-Chip Technologies, Inc.
    Inventors: Laurence Cooke, Bulent Dervisoglu
  • Patent number: 7080301
    Abstract: An integrated circuit is described that includes a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain an on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.
    Type: Grant
    Filed: October 31, 2005
    Date of Patent: July 18, 2006
    Assignee: On-Chip Technologies, Inc.
    Inventors: Bulent Dervisoglu, Laurence H. Cooke, Vacit Arat
  • Publication number: 20060064615
    Abstract: An integrated circuit is described that includes a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain an on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.
    Type: Application
    Filed: October 31, 2005
    Publication date: March 23, 2006
    Applicant: On-Chip Technologies, Inc.
    Inventors: Bulent Dervisoglu, Laurence Cooke, Vacit Arat
  • Publication number: 20060041798
    Abstract: Specific test logic may be added into a semiconductor logic or memory device, which does not change the normal operation of the device, but which allows under test mode the device to perform both parallel read-compare and parallel write operations of the blocks within the device, which provides significant reduction of the overall time to test the device.
    Type: Application
    Filed: August 23, 2004
    Publication date: February 23, 2006
    Applicant: On-Chip Technologies, Inc.
    Inventor: Laurence Cooke