Patents Assigned to Ciclon Semiconductor Device Corp.
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Patent number: 8692324Abstract: A laterally diffused metal-oxide-semiconductor transistor device includes a substrate having a first conductivity type with a semiconductor layer formed over the substrate. A source region and a drain extension region of the first conductivity type are formed in the semiconductor layer. A body region of a second conductivity type is formed in the semiconductor layer. A conductive gate is formed over a gate dielectric layer that is formed over a channel region. A drain contact electrically connects the drain extension region to the substrate and is laterally spaced from the channel region. The drain contact includes a highly-doped drain contact region formed between the substrate and the drain extension region in the semiconductor layer, wherein a topmost portion of the highly-doped drain contact region is spaced from the upper surface of the semiconductor layer. A source contact electrically connects the source region to the body region.Type: GrantFiled: June 16, 2008Date of Patent: April 8, 2014Assignee: Ciclon Semiconductor Device Corp.Inventors: Jacek Korec, Shuming Xu, Christopher Boguslaw Kocon
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Patent number: 8389336Abstract: A semiconductor die package includes: an assembly including a semiconductor die, a clip structure attached to an upper surface of the semiconductor die, and a heat sink attached to an upper surface of the clip structure; and a molding material partially encapsulating the assembly, wherein an upper surface of the heat sink is exposed through the molding material.Type: GrantFiled: September 24, 2011Date of Patent: March 5, 2013Assignee: Ciclon Semiconductor Device Corp.Inventors: Juan A. Herbsommer, Jonathan A Noquil, Osvaldo J Lopez
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Publication number: 20100176508Abstract: A semiconductor die package includes: an assembly including a semiconductor die, a clip structure attached to an upper surface of the semiconductor die, and a heat sink attached to an upper surface of the clip structure; and a molding material partially encapsulating the assembly, wherein an upper surface of the heat sink is exposed through the molding material.Type: ApplicationFiled: January 12, 2009Publication date: July 15, 2010Applicant: CICLON SEMICONDUCTOR DEVICE CORP.Inventors: Juan Alejandro Herbsommer, Jonathan A. Noquil, Osvaldo J. Lopez
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Publication number: 20100171543Abstract: A packaged switching device for power applications includes at least one pair of power MOSFET transistor dies connected between upper and lower power source rail leads, a high side one of the pair of MOSFET transistor dies being connected to the upper power source rail lead and a low side one of the pair of MOSFET transistor dies being connected to the lower power source rail lead. At least one of the MOSFET transistor dies is configured for vertical current flow therethrough and has a source electrode at a backside thereof.Type: ApplicationFiled: January 8, 2009Publication date: July 8, 2010Applicant: Ciclon Semiconductor Device Corp.Inventors: Jacek Korec, Christopher F. Bull, Juan Alejandro Herbsommer, David Jauregui, Christopher B. Kocon
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Patent number: 7745846Abstract: A semiconductor device includes a substrate having a first conductivity type and a semiconductor layer formed over the substrate and having lower and upper surfaces. A laterally diffused metal-oxide-semiconductor (LDMOS) transistor device is formed over the substrate and includes a source region of the first conductivity type and a drain extension region of the first conductivity type formed in the semiconductor layer proximate the upper surface of the semiconductor layer, and a drain contact electrically connecting the drain extension region to the substrate. A Schottky diode is formed over the substrate and includes at least one doped region of the first conductivity type formed in the semiconductor layer proximate to the upper surface, an anode contact forming a Schottky barrier with the at least one doped region, and a cathode contact laterally spaced from the anode contact and electrically connecting at least one doped region to the substrate.Type: GrantFiled: January 15, 2008Date of Patent: June 29, 2010Assignee: Ciclon Semiconductor Device Corp.Inventors: Jacek Korec, Shuming Xu, Christopher Boguslaw Kocon
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Publication number: 20090267145Abstract: A method of forming a metal-oxide-semiconductor (MOS) device includes the following steps: forming a semiconductor layer of a first conductivity type having source and drain regions of a second conductivity type, a channel region and a lightly-doped drain region formed therein; forming a gate over the channel region proximate an upper surface of the semiconductor layer; after the forming steps, depositing a first dielectric layer having a first thickness over an upper surface of the semiconductor layer; etching the first dielectric layer in a region over the lightly-doped drain proximate to the gate to reduce its thickness; conformably depositing a second dielectric layer having a second thickness over the first dielectric layer, including in the etched region, the second thickness being less than the first thickness; and forming a shielding electrode over the second dielectric layer.Type: ApplicationFiled: April 23, 2008Publication date: October 29, 2009Applicant: CICLON SEMICONDUCTOR DEVICE CORP.Inventors: Charles Walter Pearce, Simon J. Molloy, Shuming Xu, Xiao Rui Li
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Publication number: 20090179264Abstract: A semiconductor device includes a substrate having a first conductivity type and a semiconductor layer formed over the substrate and having lower and upper surfaces. A laterally diffused metal-oxide-semiconductor (LDMOS) transistor device is formed over the substrate and includes a source region of the first conductivity type and a drain extension region of the first conductivity type formed in the semiconductor layer proximate the upper surface of the semiconductor layer, and a drain contact electrically connecting the drain extension region to the substrate. A Schottky diode is formed over the substrate and includes at least one doped region of the first conductivity type formed in the semiconductor layer proximate to the upper surface, an anode contact forming a Schottky barrier with the at least one doped region, and a cathode contact laterally spaced from the anode contact and electrically connecting at least one doped region to the substrate.Type: ApplicationFiled: January 15, 2008Publication date: July 16, 2009Applicant: CICLON SEMICONDUCTOR DEVICE CORP.Inventors: Jacek Korec, Shuming Xu, Christopher Boguslaw Kocon
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Patent number: 7504733Abstract: A clip-less packaged semiconductor device includes at least one semiconductor die having bottom and top surfaces each having at least one electrode. A leadframe comprising a sheet of conductive material having top and bottom surfaces, the top surface being substantially planar, the bottom surface having a recessed region having a thickness less than the thickness of the sheet of conductive material formed in the sheet and defining a plurality of planar lead contacts, is electrically coupled to the top surface of the die at its bottom surface in the recessed region. An encapsulating layer partially encloses the leadframe and die, wherein the encapsulating layer occupies portions of the recessed region not occupied by the die, wherein the bottom surface of the die and the plurality of leadframe contacts are exposed through the encapsulating layer at least at the bottom surface of the packaged semiconductor device.Type: GrantFiled: August 17, 2005Date of Patent: March 17, 2009Assignee: Ciclon Semiconductor Device Corp.Inventor: Osvaldo Jorge Lopez
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Patent number: 7446375Abstract: A low voltage power device includes a plurality of quasi-vertical LDMOS device cells. A conductive trench sinker is formed through the epitaxial layer and adjacent a selected one of the source and drain regions in each cell. The trench sinker electrically couples the selected one of the source and drain regions to the substrate for coupling current from the channel to the substrate. The resulting device exhibits a vertical current flow between the metal electrode covering the front surface and the second electrode formed at the back side of the wafer. The device cells are arranged in a closed cell configuration.Type: GrantFiled: March 14, 2006Date of Patent: November 4, 2008Assignee: Ciclon Semiconductor Device Corp.Inventors: Shuming Xu, Jacek Korec
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Publication number: 20080246086Abstract: A laterally diffused metal-oxide-semiconductor transistor device includes a substrate having a first conductivity type with a semiconductor layer formed over the substrate. A source region and a drain extension region of the first conductivity type are formed in the semiconductor layer. A body region of a second conductivity type is formed in the semiconductor layer. A conductive gate is formed over a gate dielectric layer that is formed over a channel region. A drain contact electrically connects the drain extension region to the substrate and is laterally spaced from the channel region. The drain contact includes a highly-doped drain contact region formed between the substrate and the drain extension region in the semiconductor layer, wherein a topmost portion of the highly-doped drain contact region is spaced from the upper surface of the semiconductor layer. A source contact electrically connects the source region to the body region.Type: ApplicationFiled: June 16, 2008Publication date: October 9, 2008Applicant: CICLON SEMICONDUCTOR DEVICE CORP.Inventors: Jacek Korec, Shuming Xu, Christopher Boguslaw Kocon
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Publication number: 20080197411Abstract: A semiconductor device includes a semiconductor substrate, a first p-channel laterally diffused metal oxide semiconductor (LDMOS) transistor formed over the semiconductor substrate and additional p-channel LDMOS transistors formed over the semiconductor substrate. First drain and gate electrodes are formed over the substrate and are coupled to the first LDMOS transistor. Additional drain and gate electrodes are formed over the substrate and are coupled to the second LDMOS transistor. A common source electrode for the first and second LDMOS transistors is also formed over the substrate.Type: ApplicationFiled: February 20, 2007Publication date: August 21, 2008Applicant: CICLON SEMICONDUCTOR DEVICE CORP.Inventors: Jacek Korec, Stephen L. Colino
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Publication number: 20080036078Abstract: A wirebond-less packaged semiconductor device includes a plurality of I/O contacts, at least one semiconductor die, the semiconductor die having a bottom major surface and a top major surface, the top major surface having at least two electrically isolated electrodes, and a conductive clip system disposed over the top major surface, the clip system comprising at least two electrically isolated sections coupling the electrodes to respective I/O contacts.Type: ApplicationFiled: August 14, 2006Publication date: February 14, 2008Applicant: Ciclon Semiconductor Device Corp.Inventors: Juan Alejandro Herbsommer, George J. Przybylek, Osvaldo J. Lopez
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Patent number: 7282765Abstract: An LDMOS device comprises a substrate having a first conductivity type and a lightly doped epitaxial layer thereon having an upper surface. Source and drain regions of the first conductivity type are formed in the epitaxial layer along with a channel region of a second conductivity type formed therebetween. A conductive gate is formed over a gate dielectric layer. A drain contact electrically connects the drain region to the substrate, comprising a first trench formed from the upper surface of the epitaxial layer to the substrate and having a side wall along the epitaxial layer, a highly doped region of the first conductivity type formed along the side wall of the first trench, and a drain plug in the first trench adjacent the highly doped region. A source contact is provided and an insulating layer is formed between the conductive gate and the source contact.Type: GrantFiled: July 13, 2005Date of Patent: October 16, 2007Assignee: Ciclon Semiconductor Device Corp.Inventors: Shuming Xu, Jacek Korec
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Patent number: 7235845Abstract: A laterally diffused metal-oxide-semiconductor (LDMOS) transistor device includes a doped substrate having an epitaxial layer thereover having source and drain implant regions and body and lightly doped drain regions formed therein. The channel region and lightly doped drain regions are doped to a depth to abut the top surface of the substrate. In alternative embodiments, a buffer region of the second conductivity type and having dopant concentration greater than or equal to about the channel region is formed over the top surface of the substrate between the top surface of the substrate and the channel region and lightly doped drain region, wherein the channel region and lightly doped drain regions are doped to a depth to abut the buffer region.Type: GrantFiled: August 12, 2005Date of Patent: June 26, 2007Assignee: Ciclon Semiconductor Device Corp.Inventors: Shuming Xu, Jacek Korec
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Publication number: 20070138548Abstract: A laterally diffused metal-oxide-semiconductor transistor device includes a substrate having a first conductivity type with a semiconductor layer formed over the substrate. A source region and a drain extension region of the first conductivity type are formed in the semiconductor layer. A body region of a second conductivity type is formed in the semiconductor layer. A conductive gate is formed over a gate dielectric layer that is formed over a channel region. A drain contact electrically connects the drain extension region to the substrate and is laterally spaced from the channel region. The drain contact includes a highly-doped drain contact region formed between the substrate and the drain extension region in the semiconductor layer, wherein a topmost portion of the highly-doped drain contact region is spaced from the upper surface of the semiconductor layer. A source contact electrically connects the source region to the body region.Type: ApplicationFiled: February 20, 2007Publication date: June 21, 2007Applicant: CICLON SEMICONDUCTOR DEVICE CORP.Inventors: Christopher Kocon, Shuming Xu, Jacek Korec
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Patent number: 7166496Abstract: A clip-less packaged semiconductor device includes at least one semiconductor die having bottom and top surfaces each having at least one electrode. A leadframe comprising a sheet of conductive material having top and bottom surfaces, the top surface being substantially planar, the bottom surface having a recessed region having a thickness less than the thickness of the sheet of conductive material formed in the sheet and defining a plurality of planar lead contacts, is electrically coupled to the top surface of the die at its bottom surface in the recessed region. An encapsulating layer partially encloses the leadframe and die, wherein the encapsulating layer occupies portions of the recessed region not occupied by the die, wherein the bottom surface of the die and the plurality of leadframe contacts are exposed through the encapsulating layer at least at the bottom surface of the packaged semiconductor device.Type: GrantFiled: September 9, 2005Date of Patent: January 23, 2007Assignee: Ciclon Semiconductor Device Corp.Inventors: Osvaldo Jorge Lopez, Mark Henry S. Antiporta, Fernando V. Capinig, Ricky B. Calustre, Emmievel S. Anacleto, Mizpa B. Mijares
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Publication number: 20070007593Abstract: An MOS device is formed including a semiconductor layer of a first conductivity type, a first source/drain region of a second conductivity type formed in the semiconductor layer, and a second source/drain region of the second conductivity type formed in the semiconductor layer and spaced apart from the first source/drain region. A gate is formed proximate an upper surface of the semiconductor layer and at least partially between the first and second source/drain regions. The MOS device further includes at least one contact, the at least one contact including a silicide layer formed on and in electrical connection with at least a portion of the first source/drain region, the silicide layer extending laterally away from the gate. The contact further includes at least one insulating layer formed directly on the silicide layer.Type: ApplicationFiled: September 15, 2006Publication date: January 11, 2007Applicant: CICLON SEMICONDUCTOR DEVICE CORP.Inventors: Frank Baiocchi, Bailey Jones, Muhammed Shibib, Shuming Xu
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Patent number: 7126193Abstract: An MOS device is formed including a semiconductor layer of a first conductivity type, a first source/drain region of a second conductivity type formed in the semiconductor layer, and a second source/drain region of the second conductivity type formed in the semiconductor layer and spaced apart from the first source/drain region. A gate is formed proximate an upper surface of the semiconductor layer and at least partially between the first and second source/drain regions. The MOS device further includes at least one contact, the at least one contact including a silicide layer formed on and in electrical connection with at least a portion of the first source/drain region, the silicide layer extending laterally away from the gate. The contact further includes at least one insulating layer formed directly on the silicide layer.Type: GrantFiled: September 29, 2003Date of Patent: October 24, 2006Assignee: Ciclon Semiconductor Device Corp.Inventors: Frank A. Baiocchi, Bailey R. Jones, Muhammed Ayman Shibib, Shuming Xu