Abstract: An improved logic simulation system including a logic simulator which provides the logic states of elements within an electronic circuit being analyzed, means for associating the logic states with a schematic image of the electronic circuitry for display on a visual display device, wherein the improvement includes means for designating the color of the element being displayed which color represents the logic state of the element for a selected point in time.

Abstract: In a system for generating tests for digital circuits, a fault simulator (16) simulates a fault-free version of the circuit and all expected faulty versions of it concurrently, basing its operation on information contained in a data base (12) that contains information about the structure and possible defects of the circuits to be tested. A waveform system (14) carries high-level information regarding the general structure of the test waveform that ultimately is to be derived, such as clock signals, timing constraints, and other restrictions that the designer of the circuit under test has placed on the signals to be applied to it.