Abstract: A latch transfers fetched opcode to PLA for execution at the earliest opportunity following execution of a prior single cycle opcode.

Abstract: A fast logic gate wherein the gate output assumes a first binary state when two or more of the gate inputs assume the same predetermined binary states and wherein the gate output assumes a second binary state otherwise. The delay in propagating the gate output based on a transition at a predetermined one of the gate inputs is relatively small. In a preferred application, the gate is utilized in a microprocessor ALU, more particularly, the portion of each adder bit which generates the carry output, and the predetermined gate input is the carry input of the adder bit. The microprocessor can therefore execute instructions which involve addition or subtraction operations, such as relatively addressing instructions, much more quickily.

Abstract: A computer system mouse-type input device. Movements of a track-ball motion sensor are converted to quadrature signals and are accumulated in a counting circuit. The contents of the counter are pulse-position modulated with waveforms characteristic of a resistive-capacitive charging circuit and are read periodically by a computer input channel normally used for input of potentiometer-generated commands. The pulse-position modulated signals are converted to digital values used by the computer to position the cursor on a display screen.

Abstract: A computer video demultiplexer for combining a plurality of low resolution, video input signals into a plurality of higher horizontal and vertical resolution video output signals. Control signals for the video demultiplexer are coded on non-displayed video scan lines which are uniquely addressable so that several demultiplexers operated from one video signal may control a number of high resolution peripheral devices.

Abstract: A monitoring circuit incorporated into a video game display device is operated responsively to first and second non-overlapping clock pulses and monitors raster line status in comparison to a stored raster address and provides a high speed raster scan interrupt when that address is achieved, triggering a SPRITE or other feature(s) display.

Abstract: A n-channel memory management circuit operates as an interface unit between a microprocessor, which microprocessor is normally capable of addressing only 64K bytes of memory, to provide expandable memory configurations with a memory capacity of at least 128K bytes of read only memory (ROM) and 128K bytes of random access memory (RAM) which are directly accessed by the microprocessor in 64K bytes blocks or "windows" consisting of smaller size non-contiguous blocks from the entire memory configuration.

Abstract: A current mirror amplifier is provided wherein the feedback path around a diode-connected device is modified by adding a resistor in series with the input terminal of the diode-connected device in order to cancel a pole which appears at the unity-gain frequency. This will improve the frequency response and provide for increased bandwidth. The added resistor may be realized in MOS technology by employing a tracking MOS device.

Abstract: A sound interface circuit is implemented in large scale integrated circuitry (LSI) on a single chip to provide 3 voice electronic music synthesizer/sound effects, and is compatible with instructions from commercially available microprocessors; whereof a wide range, high-resolution control of pitch (frequency) tone color (harmonic content) and dynamics (volume) is achieved and specialized control circuitry minimizes software overhead, facilitating use in arcade/home video games and low cost musical instruments.

Abstract: A solid state logical "OR" circuit for implementation with NMOS circuitry has self-booting clock pulse conditioning for ultra fast propagation times and minimal power dissipation, whereof memory row driver concepts are utilized and silicon area is minimized.

Abstract: A comparator circuit incorporated into a video game device and operated responsive to first and second non-overlapping clock pulses can be used to compare background information location to SPRITE information location for both raster line (vertical) and column (horizontal) coordinates to provide a high speed interrupt signal to a central processor unit (CPU) triggering a processing of SPRITE or other features' display instead of a processing of background display, the comparator being implemented in less silicon area and having a lower power usage than other types of circuit implementations.

Abstract: A solid state logical "AND" circuit implementation in NMOS circuitry has clock pulse conditioning providing self booting voltage levels for ultra fast propagation times and minimal power dissipation, where memory row driver concepts are utilized and silicon area is minimized, and two, low impedance, non-overlapping clock pulses, normally present in the environment are utilized.

Abstract: Programmable I/O (input/output) interface circuitry provides video and audio signals, needed for a video computer/game, to a commercial color television type display/monitor and may be implemented in HMOS, (H type metal oxide semiconductor) large-scale-integrated circuitry. The system architecture allows for reduced chip count, and improved reliability while providing adequate synchronization pulses, luminance level signals, chrominance phase shift signals, raster control and cursor control video and three independently controlled audio voices. A software selectable keyboard latch input, plural speed processing for faster operation when outside the active display area or during blanking, all system control signals necessary for system operation and 3 independently controlled interrupt generating timers are also provided.

Abstract: A display control circuit provides the logical determination of display information for each dot point of a color television or other display device used in connection with an electronic game for displaying up to eight "targets", as well as background information, according to a preassigned software defined priority whereby hardware circuitry encodes background-to-target software information and then decodes all game display circuit information to generate a color display code to the color television-type display device, this hardware utilizing a reduced space on a large scale integrated (LSI) circuit.

Abstract: A solid state logical "EXCLUSIVE OR" circuit for implementation in NMOS circuitry utilizes existing non-overlapping clock pulses for self-booting circuit conditioning, enabling ultrafast propagation times and minimal power drain during circuit operation, whereof row driver circuit design concepts are utilized and silicon area is minimized and two, non-overlapping, low impedance pulses, normally present in the circuit environment are utilized.

Abstract: A solid-state, digital logic, sine-cosine generator is provided for use in color television signal generators which contributes little or no phase shift or drift, whereby an input frequency of four times the color burst rate is used, and a first divide by two shift register operates upon that input signal frequency while a second divide by two shift register is used to obtain the proper color burst frequency as well as the 90.degree. relationship for the sine and cosine signals; a series of integrators then converts the digital "square" waves to triangular and then sinusoidal signals.