Abstract: A system and method for performing secure peer-to-peer device communications on an I/O bus, such as a PCI bus, a Fiber Channel bus, an IEEE, 1394 bus or a Universal Serial Bus. The system includes a plurality of intelligent I/O devices, such as intelligent storage devices and/or controllers, communications devices, video devices and audio devices. The I/O devices perform peer-to-peer message and data transfers, thereby bypassing the operating system running on the computer's CPU. The intelligent I/O devices encrypt messages and data before transmitting them on the I/O bus and conversely decrypt the messages and data upon reception. The encryption provides secrecy and/or authentication of the sender. The devices use keys or passwords to encrypt/decrypt the data. The keys are stored in non-volatile memory in the devices and are distributed to the devices by the system BIOS at initialization time.

Abstract: A method for use in a computer system having buses identifiable by bus identifiers and having an expansion card slot capable of being connected to one of the buses and capable of receiving an expansion card. The method includes assigning the bus identifiers to the buses according to an assignment sequence. The method determines if there is an expansion card that can be accessed via the slot. If not, at least one of the bus identifiers for the slot is reserved in accordance with the assignment sequence. Memory space and I/O space may also be reserved for the slot if the expansion card cannot be accessed.

Abstract: A method is provided for creating a virtual operating system directed power management event. The method may include executing a prepare-to-sleep routine in a computer system running an Advanced Configuration and Power Interface (ACPI) compliant operating system. The prepare-to-sleep routine may include programming ACPI compliant core logic such as the Intel PIIX4 device to generate an I/O trap system management interrupt (SMI) upon accesses to the ACPI WAK.sub.-- STS register. The prepare-to-sleep routine may also enable non-dedicated event signals, such as legacy IRQs, to serve as resume events. After a resume event, the operating system reads the WAK.sub.-- STS register. Upon access to the WAK.sub.-- STS an SMI is generated. An SMI handler may be executed that determines if the resume event was generated by a wake device.

Abstract: A computer is provided having a memory system supporting page mode accessing. A memory controller may be provided in a bus interface unit coupled between a CPU bus, and a mezzanine bus, or PCI bus. The memory controller includes logic that provides for dynamic management of page accessing. The memory controller may include logic for monitoring the page hit:precharge ratio for accesses to system memory and dynamically switch between a paging state of operation and an auto-precharge state of operation according to the hit:precharge ratio. A configuration register may be provided to select dynamic mode in which the memory controller dynamically enables/disables paging to improve performance. The configuration register may also be programmed to manually enable/disable paging. The memory controller may include a page table for tracking open pages. The system memory may include SDRAM devices.

Abstract: An apparatus is provided for coupling a printed circuit board within a printed circuit board cage. The apparatus includes a baseplate and a latch. The baseplate is mounted to the printed circuit board. The latch is rotatably coupled to the baseplate. The latch includes a pivoting portion, a shaft, and a swell nut. The pivoting portion includes an ejector extending from an end of the pivoting portion. The ejector is engageable with the printed circuit board cage. The shaft is coupled to the pivoting portion. The swell nut is coupled to the shaft and engageable with the printed circuit board cage.

Abstract: A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU. The vector instructions employ special load/store instructions in combination with numerous operational instructions to carry out concurrent multimedia operations on the aligned operands.

Abstract: A computer system comprising a display monitor including an audio function and a computer coupled to the display monitor including a computer controller for controlling the audio function in the monitor. The computer is operable in a computer mode, a television mode, and a combination computer/television mode for displaying computer and television information on the monitor. The system determines whether the monitor includes a controller for controlling its audio function. Based upon this determination, the system controls the audio function with the audio controller in the monitor if the monitor includes such a controller or, alternatively, with the computer controller if the monitor does not have such a controller.

Abstract: A computer is provided having a bus interface unit which is coupled between a peripheral bus and a dedicated graphics bus. The graphics bus can be linked to the bus interface unit by an AGP, while the peripheral bus can be linked to the bus interface unit by a PCI. Arbitration for the AGP bus can determine when mastership is granted to an AGP master (i.e., graphics accelerator/controller). Until mastership is granted, the AGP target is powered down to a low power state where power consumption within the bus interface unit is minimal. It is not until the AGP master achieves mastership that the graphics target (core logic and memory controller) within the bus interface unit is placed in an operational (fully powered) state. The computer therefore employs a bus interface unit which can be dynamically switched from a high power state to a low power state and vice versa, depending upon accesses to the graphics target.

Abstract: A computer system in which various system peripherals are automatically re-initialized after being hot-swapped. The reinitialization includes accommodation of any required master/slave relationships between the peripherals.

Abstract: A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU. The vector instructions employ special load/store instructions in combination with numerous operational instructions to carry out concurrent multimedia operations on the aligned operands.

Abstract: A system for allowing a peripheral device to be inserted directly into a port of a computer system while the computer system is powered on. The insertion of a peripheral device into the computer system port is automatically detected, and a configuration operation is automatically performed when insertion of the peripheral device is detected. The system also allows a plurality of peripheral devices to be connected to a single port of a computer system by automatically determining the number of peripheral devices and assigning a unique address to each of the peripheral devices. The peripheral device may have a host port for communicating with the computer system, a slave port for connecting to a slave device, and a device manager which identifies if a slave device is connected.

Abstract: A remote control input device for use with a computer system is disclosed. The remote control input device typically includes means for wirelessly connecting the remote control input device to the computer system, a trackball, coupled to the connecting means for manipulating a pointing icon displayed on the video monitor, and a power source that powers the remote control input device. The remote control input device further includes a power management means for managing the power of the power source by monitoring the status and activity of the trackball used on the remote control input device. The remote control input device typically includes a first set of keys that provide input to the computer system and a second set of keys that are assigned to the trackball that control the pointing icon manipulated by the trackball.

Abstract: A computer network system having a plurality of nodes, one of which is adapted as an administrator node, the administrator node for securely receiving code information from a code provider disposed external to the network system and for securely sending the code information to at least one of the nodes.

Abstract: An object-driven application tool allows a Value Added Reseller (VAR) to access a large body of publicly available information about computing devices and to identify the needs of a particular customer or end user and to select an appropriate solution of equipment, hardware, and networking products to meet the customer's needs. Moreover, the tool includes capabilities allowing a VAR to demonstrate to the end user the appropriateness of the solution, for allowing information entry in high level, abstract business-oriented vocabulary rather than a highly technical low level jargon (thus facilitating data entry of information obtained from the end user) and allowing the tool to recognize whether, for example, a slight increase in memory capacity beyond the express needs of the end user may allow a dramatic reduction in requirements for processor speed or non-volatile data storage.

Abstract: A modular computer chassis configurable for both rack mounting and free standing use includes a housing with a multiple compartments for receiving computer devices and peripherals therein. The housing further includes side access panels and a top access panel, each being attachable and removable from the frame of the chassis without tools. The frame of the modular computer chassis is configured with slots to receive corresponding tabs on each of the side and top panels which facilitate the quick installation and removal of the side and top panels from the frame of the chassis. Multiple tool-less fasteners are used to further secure side and top covers to the frame of the chassis.

Abstract: A page-wide, drop-on-demand type ink jet printhead and an associated method of manufacturing an orifice plate. The orifice plate is comprised of a block of material in which a first portion of the block of material has been removed to define an ink reservoir. Also formed in the orifice plate are a series of apertures, each of the apertures includes an ink jet and an ink jet nozzle. A fill channel, which extends between the ink reservoir and each ink jet, is also formed in the orifice plate to provide a supply of ink to the ink jet. An intermediate layer is mounted to the orifice plate. The intermediate layer is formed of an active piezoelectric material and a series of piezoelectric actuators, each acoustically coupled to a corresponding one of the series of apertures, are formed on the intermediate layer.

Abstract: A computer system with a plurality of devices compatible with the Fibre Channel Protocol. The computer system is provided with the capability to recover from a loop hang condition resulting from an unresponsive communication link in an Arbitrated Loop. This capability is realized by providing a sense mechanism for detecting a no-change condition in the states associated with a controller arranged in the Arbitrated Loop.

Abstract: In a computer system having redundant power supplies, an I.sup.2 C data bus architecture it utilized to provide communication between the power supplies and other computer peripherals connected to the I.sup.2 C bus. A switch separates the power supplies from the other peripheral devices, such that the switch, when open, isolates the power supplies from the other devices, so that during power-up the power supplies can communicate over the I.sup.2 C bus. When the switch is closed, the switch becomes transparent and connects the peripherals with the power supplies over the I.sup.2 C bus.

Abstract: A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU. The vector instructions employ special load/store instructions in combination with numerous operational instructions to carry out concurrent multimedia operations on the aligned operands.

Abstract: A multiple use core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port ("AGP") bus and host and memory buses, as a bridge between an additional registered peripheral component interconnect ("RegPCI") bus and the host and memory buses, or as a bridge between a primary PCI bus and an additional RegPCI bus. The function of the multiple use chip set is determined at the time of manufacture of the computer system or in the field whether an AGP bus bridge or an additional registered PCI bus bridge is to be implemented. The multiple use core logic chip set has an arbiter having Request ("REQ") and Grant ("GNT") signal lines for each PCI device utilized on the additional registered PCI bus. Selection of the type of bus bridge (AGP or RegPCI) in the multiple use core logic chip set may be made by a hardware signal input, or by software during computer system configuration or power on self test ("POST").