Abstract: The present invention reduces the compile time in a top-down rule based system by identifying the complexity of a query prior to applying a rule to an expression. If the complexity of the query is above a threshold, the present invention determines whether the rule should be applied based upon several factors including the type of rule and the position of the node in the search space. Those rules that need not be applied are randomly pruned at a determined rate that prevents search space explosion and prevents the elimination of large contiguous portions of the search space. Pruned rules are not applied, while those rules that are not pruned are applied.

Abstract: A multiplier including a processor that generates at least one N by M array of partial products. The processor includes a first section that performs a first operation that generates an N by M array of partial products representing low order bits, and a second section that performs a second operation that generates an N by M array of partial products representing high order bits. The multiplier also includes a compressor that compresses the N by M array of partial products representing low order bits after the first operation and generates a plurality of carry bits that are utilized in the second operation.

Abstract: A technique for locating objects within an image is disclosed. In one embodiment, the technique is realized by obtaining an image and then identifying an object within the image based upon an orientation of the object within the image. The image can be a representation of a plurality of pixels, wherein the plurality of pixels are arranged in a plurality of columns and rows, and wherein at least some of the plurality of pixels are enabled to represent the object.

Abstract: A network switch includes a plurality of first network ports coupled to a first bus, a plurality of second network ports coupled to a second bus, a bridge interface enabling data transfer between the buses, a switch manager controlling the flow of network data, and a processor for performing supervisory and control functions. The first and second network ports operate according to different network protocols, and the first and second buses operate according to different bus standards. During packet data transfers across the first bus, the bridge interface emulates a first network port. During packet data transfers across the second bus, the bridge interface primarily acts as a slave to the second network ports by storing control lists for execution by the second network ports, thus relieving the processor of performing overhead functions associated with data transfers across the second bus.

Abstract: A computer system includes memory modules, a central processing unit and a memory controller. The memory controller is configured to access the memory modules in response to interaction with the central processing unit and define a fault tolerant memory array with the memory modules. Each memory module stores first data represented by second data stored by the other memory modules.

Abstract: Schemes for customization of content presentation relating to a Digital Versatile/Video Disc source, which source is preferably integrated into a convergence device system. A user preferences or settings database is provided that is automatically maintained or supported by a computer subsystem, wherein records containing user preference values are indexed to a DVD title or volume having an identity tag. Changed values are also stored and applied during the next playback of the title. The present invention also provides a censor block database structure containing individualized viewing sequences from a title for different users with different levels of censorship.

Abstract: An embodiment of the present invention provides a method and apparatus for sorting very large data sets using a parallel merge sort. Given sorted work files S1, . . . , Sp, produced by P processes, the described embodiment of the method effectively implements a parallel merge onto respective output partitions O1, . . . , Op of the processes P. Because each of these output partitions O has a finite size, the invention must quickly determine “splitting keys” for each output partition O in such a way that the data in the work files will be split between the multiple output partitions O without overrunning the size of any of the partitions O. Once the splitting keys for each partition are determined, the processes exchange data so that the output partitions of each process contains data between the splitting keys associated with that output partition.

Abstract: A biased arbitration technique utilizes a transpose table to arbitrate access to a shared resource. Each column of transpose table is a binary bias vector encoding a bias value assigned to one of the requesters. The rows of the table are fetched to assure that requesters having high bias values are granted more frequent access to the shared resource.

Abstract: A short circuit protection device, which includes a comparator with a non-inverting input port, an inverting input port, and an output port, is used with first and second voltage reference signals obtained from a power supply to indicate a short-circuit condition in the power supply when the reference signals are the same. A first voltage divider is connected to the power plane of the power supply and provides the first reference signal to the non-inverting input port, and a second voltage divider is connected to the output port of the power supply and provides the second reference signal to the inverting input port, where the second reference signal is normally smaller than the first reference signal.

Abstract: A system for facilitating the mounting of circuit boards within an enclosure. The system includes one or more standoffs that are each received through appropriately formed corresponding openings through a printed circuit board. A flexible clip is attached to the printed circuit board proximate each opening. Each clip includes a retainer portion designed to receive the head of the standoff. Thus, the printed circuit board may be attached to the standoffs simply by placing the circuit board openings over the standoffs and moving the printed circuit board laterally until the clips and standoffs are engaged.

Abstract: A system and method that implement a strategy for automatically generating self-checking tests of source-to-source translation. The tests make certain that software components produced by a source-to-source computer language translator continue to be binary-compatible with all other software components with which they previously interacted correctly, including components that remain in the original programming language. To that end, the correctness of procedure interfaces in a target computer program is also verified. With this strategy, correct translation of text preprocessor mechanisms such as macros, conditionally compiled regions of code, and source file inclusion can be achieved. The target program is the result of translating a source program written in a different language from the target program. The system creates a set of procedure calls to each procedure in the source program. The system also creates a set of callable procedures with the same interface specification as in the source program.

Abstract: A system for protecting circuit board mounting devices within an enclosure. The system includes one or more protective housings that are disposed about corresponding openings through a printed circuit board. A flexible clip is attached to the printed circuit board proximate each opening. Each clip includes a retainer portion designed to receive the head of the standoff. The protective housings extend around the retainer portion, and protect the secure mounting of the circuit board to corresponding standoffs.

Abstract: An apparatus generates one-dimensional dither values for dithering linear digital signals where each digital signal having an address and a signal value. The apparatus includes a counter incremented for each sequential address of the digital signals. A predetermined number of least significant bits from the current values of the counter are selected and reversed wired to generate dither values that are applied to the corresponding signal values.

Abstract: A technique for differencing an image is disclosed. In one embodiment, the technique is realized by measuring light values in a scene to generate a first image and a second image. The first image is separated into first luminance and chrominance components, and the second image is separated into second luminance and chrominance components. A difference is determined between the first and the second luminance components to generate a luminance mask. Similarly, a difference is determined between the first and the second chrominence components to generate a chrominance mask. The luminance mask and the chrominence mask are combined to determine a difference between the first and the second images.

Abstract: A digital imaging system is provided for interpolating a full color image from a camera having an array of single color sensors. Measured color values are stored as an array of data elements in a memory of the system. Each data element corresponds to the measured color value from one sensor. A set of gradient values is determined for each data element at a specific location in the array. The gradient values correspond to color value differences in a plurality of directions from the data element. From the set of gradient values, a threshold value is determined. Using the threshold value, a subset of gradient values is selected so that the members of the subset have gradient values less than the threshold. Additional color values for each data element are interpolated according to the subset of gradient values.

Abstract: A screwless technique for mounting a circuit board in a computer chassis is provided in which circular portions of keyhole-shaped mounting openings in the circuit board body are first moved downwardly over notched chassis mounting bosses. The circuit board is then forwardly moved transversely to the bosses to move opening edge portions of the circuit board body into the boss notches in a manner releasably preventing the circuit board from being lifted off the bosses. A retaining bracket is placed adjacent a body edge of the installed circuit board to block the board against rearward releasing movement relative to the chassis bosses.

Abstract: A highly reliable computer memory storage system that is divided into subsystems, each of which is provided in triplicate: a primary subsystem, a backup subsystem and a spare subsystem. Upon detection of a non-recoverable failure in a primary subsystem, the backup subsystem substantially immediately assumes the tasks of the primary subsystem while the spare subsystem is integrated into the operation of the computer memory storage system. The triple replication of all subsystems and mechanisms for detecting failures in at least the primary and secondary subsystems provides an overall memory system which is highly reliable and substantially never requires servicing. In an alternative embodiment, three subsystems can share a load equally, for example a cooling or power supply load requirement.

Abstract: A method, apparatus and computer system for correcting errors and defects in a storage device. The storage device includes media for storing data. A periodic read scan is performed to test the data. If a repeatable error is found, the data is moved to a new sector from a pool of available sectors. Defects are counted and identified in a defect list for reporting to the host. The storage device is scannable is small segments to minimize impact on performance.

Abstract: A protocol for a transaction involving two homogeneous or two heterogeneous computing systems involves starting a transaction on one of the two systems, sending a request for participation in the transaction to an application resident on the other of the two systems, together with an identification and address of the transaction. Upon receipt of the request, the application will initiate a subordinate transaction through a resident (subordinate) transaction manager. The subordinate transaction manager will notify the Beginner transaction manager and at the same time cause the application to start work on the request. Later, the subordinate transaction, through the subordinate transaction manager participates in a two-phase commit protocol that concludes the transaction to ensure that all changes effected by the transaction are done, or none are done, i.e., the transaction is aborted.

Abstract: A system and method for dynamically allocating memory in a computer system at the application level. The application examines a heap data structure and a free list, identifies an unallocated region of memory that is appropriately sized, and allocates the memory to the application. The application deallocates a memory region by placing the memory region in the free list and modifying the heap data structure.