Abstract: Large amounts of multimedia data are transmitted over information networks in the form of a digital stream, analog video, or text captioning. Often, repetitions such as paid advertisements, theme music at the commencement of a TV broadcast, and common jingles and slogans occur in these streams. Detection of repetitions in a transmitted signal such as streaming audio or video is described, and includes extracting a plurality of samples from the information stream and accumulating the samples into segments comprising an interval of the transmitted signal. A vector indicative of the samples in each of the segments is generated, and each of the vectors in the segments is correlated to generate a covariance matrix, or signature, corresponding to the segment. Each of the covariance matrices are aggregated into a sequence of covariance matrices and compared to other covariance matrices to generate a distance matrix.

Abstract: Media slides are often employed in conference sessions, meetings, lectures, and other interactive forums. The proliferation of laptops and handheld computers allows a speaker to present directly from the laptop by connecting to the projector at the conference site. Physically connecting and disconnecting each presenter's laptop to the projection apparatus, however, can be a clumsy and disruptive process, particularly since the presenters may be seated at various locations around the room. A wireless interface between a presentation server and a laptop in a multi-user multi-projector presentation system allows a media sequence from each media source to be displayed on a common display via the presentation server and the wireless interface. Presenters need not run or swap cables or other physical connections to switch media sources to the common display. The interface requires no software modification to the media source laptops and maintains independence between media sources and the server for security.

Abstract: A digital modem for operating in a splitterless environment that supports fast retrain based on communication profiles. The modem includes a memory that stores a plurality of communication profiles, ADSL communication logic that sends and receives information via a phone line and that operates according to any one of the plurality of communication profiles, and signal quality monitor logic that continuously monitors communication on the phone line. The monitor logic provides a signal change indication if the signal quality changes by at least a predetermined amount. The modem further includes fast retrain logic that selects another one of the profiles stored in the memory in response to the signal change indication, that retrains the communication logic to operate according to the selected profile and that cooperates with the communication logic to transmit a fast retrain indication via the phone line to the central office ADSL modem.

Abstract: A core logic chip set is provided in a computer system to provide a bridge between host and memory buses and an accelerated graphics port (“AGP”) bus adapted for operation of two AGP devices, or one AGP device and one peripheral component interconnect (“PCI”) device. A common AGP bus having provisions for the PCI and AGP interface signals is connected to the core logic chip set and the AGP and/or PCI device(s). The core logic chip set has an AGP/PCI arbiter having Request (“REQ”) and Grant (“GNT”) signal lines for each AGP and/or PCI device connected to the AGP bus. Another embodiment has a plurality of AGP buses for a plurality of AGP devices. This allows concurrent operation for AGP devices connected to different AGP buses. Two of the AGP buses may be combined to connect to one 64 bit PCI device.

Abstract: The present invention relates to a method and apparatus that minimizes shock/vibrational motion in interposer sockets. The ability to control shock/vibration can ensure successful operation and substantially increase socket lifetime. The present invention discloses a device for maintaining a heat sink in a desired relationship to a mounting base while limiting the transmission of shock and vibrational motion to and from the heat sink includes a fastener extending from the mounting base, a spring compressed between the fastener and the heat sink, and a damper compressed between the fastener and the sink wherein the fastener maintains the spring and the damper in a compressed state such that the spring and the damper bear on said heat sink.

Abstract: A networking modem capable of full duplex communication over a telephone line is adapted for use as a component of a computer system. The modem comprises a digital signal processor (DSP) capable of implementing a plurality of digital modulation and demodulation techniques, including pulse position modulation (PPM), quadrature phase shift keying (QPSK), and quadrature amplitude modulation (QAM). The DSP implements a digital phase locked loop (DPLL), including a carrier NCO and a carrier detector to synchronize local demodulation timing to an incoming carrier signal. Available processing options include spectral agility for optimizing channel capacity, symbol shaping to compensate for evolving channel conditions, and echo cancellation.

Abstract: In accordance with the present invention a method is provided for managing TCP port numbers used by applications running on a cluster. Using that method, ranges of TCP port numbers are locked (reserved) by a processor node of a cluster. An application running on one of those processor nodes uses a locked TCP port number when issuing a data packet that includes the cluster alias address as the source address. With such an invention, applications running on each processor node within a cluster will use unique TCP port numbers when using the cluster alias address. Therefore, connections between a source and destination application can be uniquely registered at the destination processor node using an index formed by a combination of the source address and the TCP port number with the destination address and TCP port number.

Abstract: A heat sink assembly for use with edge connectors, e.g., card edge connectors, of cards or printed circuit boards. The heat sink assembly provides a relatively large heat transfer capacity to control temperatures in contacts of the edge connectors which increases the current rating of the connector by allowing more current to pass through the connector. The heat sink assembly includes fins attached to the edge connector power and ground leads by direct thermal connection, such as soldering, to traces in the board. The fins are connected to the power and ground leads in an alternating or interweaved fashion. The fins are fabricated from thermal conducting material and heat is conducted to the fins where it is removed by the relatively large surface area of the fins. Adjacent fins are electrically isolated such that power and ground fins do not contact.

Abstract: A computer system contains a processor that includes a software programmable memory mapper. The memory mapper maps an address generated by the processor into a device address for accessing physical main memory. The processor also includes a cache controller that maps the processor address into a cache address. The cache address places a block of data from main memory into a memory cache using an index subfield. The physical main memory contains RDRAM devices, each of the RDRAM devices containing a number of memory banks that store rows and columns of data. The memory mapper maps processor addresses to device addresses to increases memory system performance. The mapping minimizes memory access conflicts between the memory banks. Conflicts between memory banks are reduced by placing a number of bits corresponding to the bank subfield above the most significant boundary bit of the index subfield.

Abstract: Multiple instances of operating systems execute cooperatively in a single multiprocessor computer wherein all processors and resources are electrically connected together. The single physical machine with multiple physical processors and resources is subdivided by software into multiple partitions, each running a distinct copy, or instance, of an operating system. Each of the partitions has access to its own physical resources plus resources designated as shared. The partitioning is performed by assigning all resources with a configuration tree. None, some, or all, resources may be designated as shared among multiple partitions. Each individual operating instance will generally be assigned the resources it needs to execute independently and these resources will be designated as “private.” Other resources, particularly memory, can be assigned to more than one instance and shared.

Abstract: A computer system, bus interface unit, and method are provided for securing certain Plug and Play peripheral devices connected to an ISA bus. Those devices include any device which contains sensitive information or passwords. The device may be encompassed by or interfaced through adapter cards which can be readily inserted into sockets and thereafter relocated to dissimilar sockets. A security device within the bus interface unit keeps track of identifying information of various Plug and Play ISA devices inserted and re-inserted into slots connected to the ISA bus. As a peripheral device or card is moved, an identifying number associated with that device is maintained in a device identification register within the bus interface unit. Moreover, the base address of that device address space is also maintained in I/O address registers contained within the bus interface unit. The device identification registers and I/O address registers are deemed shadowing registers to which future ISA cycles are compared.

Abstract: A computer system has a USB bus to which one or more USB-compatible devices can connect. One or more of the USB devices has an electrical interface that includes two transmitters and, if desired, a receiver for bidirectional data transmission. The transmitters preferably are dual output, differential transmitters. The transmitters include a slower transmitter and a faster transmitter. The faster transmitter can transmit data at a rate that is faster than the slower transmitter. The electrical interface also includes an electrical termination device that is disposed between the output terminals of the two transmitters. The termination device preferably comprises a pair of multi-purpose termination resistors that can provide serial termination or parallel termination depending whether the fast or slow transmitter is used.

Abstract: A protocol for a transaction involving two homogeneous or two heterogeneous computing systems involves starting a transaction on one of the two systems, sending a request for participation in the transaction to an application resident on the other of the two systems, together with an identification and address of the transaction. Upon receipt of the request, the application will initiate a subordinate transaction through a resident (subordinate) transaction manager. The subordinate transaction manager will notify the Beginner transaction manager and at the same time cause the application to start work on the request. Later, the subordinate transaction, through the subordinate transaction manager participates in a two-phase commit protocol that concludes the transaction to ensure that all changes effected by the transaction are done, or none are done, i.e., the transaction is aborted.

Abstract: A computer system for executing a binary image conversion system which converts instructions from a instruction set of a first, non native computer system to a second, different, native computer system, includes an run-time system which in response to a non-native image of an application program written for a non-native instruction set provides an native instruction or a native instruction routine. The run-time system collects profile data in response to execution of the native instructions to determine execution characteristics of the non-native instruction. Thereafter, the non-native instructions and the profile statistics are fed to a binary translator operating in a background mode and which is responsive to the profile data generated by the run-time system to form a translated native image. The run-time system and the binary translator are under the control of a server process.

Abstract: Apparatus and method are disclosed for down scaling performance of a multibus multiprocessor computer system. One or more busses associated with one or more failed processors or devices are disabled to allow operation from remaining busses. If errors or power failure are detected in a processor or bus device the computer system may reboot and, using the apparatus and method of the present invention, the bus associated with the defective processors or devices may be disabled upon reboot. The one or more affected busses may be disabled and the computer system may be brought back up in a single-bus operational mode or a multiple bus operational mode where an alternate bus is designated as the boot bus.

Abstract: A memory controller capable of supporting heterogeneous memory configurations enables seamless communications between a bus and memory modules having different characteristics. Thus, owners of computer systems need no longer replace entire memory arrays to take advantage of new memory modules; some memory modules may be upgraded to a new type while other memory modules of an older type remain. The memory controller receives memory requests from multiple processors and bus masters, identifies a memory module and memory access parameters for each request, accesses the memory and returns the resulting data (during a read request) or stores the data (during a write request). In some systems, the memory controller of the present invention is a two-tier memory controller system having a first memory controller coupled to the bus and to the second tier of memory controllers or RAM personality modules that translate between the first memory controller and a particular type of memory module.

Abstract: A multiphase IEEE 1394 network of nodes requires all nodes to broadcast their current understanding of the phase of the bus (e.g., odd or even). Even if a node is not requesting ownership of the bus, it must send a message that indicates which phase that node believes to be the current phase of the network. If a node that does not need ownership of the bus believes the bus currently is in the odd phase, then that node will transmit a “None_odd” message indicating the node's understanding that the bus is in the odd phase. Similarly, if a node that does not need the bus believes the bus currently is in the even phase, then that node will transmit a “None_even” message indicating the node's understanding that the bus is in the even phase. Preferably, the current bus owner will not switch the phase of the bus until all nodes have a correct understanding of the current phase of the bus.

Abstract: A conditional clock gate is implemented that equalizes load conditions on clocked transistor gates to provide a better quality clock signal in a clock distribution network. The conditional clock gate may be implemented as either a NAND gate or a NOR gate. According to one embodiment, a pre-charge transistor is that equals clock loading when the enable signal is de-asserted. The pre-charge transistor charges a terminal of a clocked transistor during certain clock states to mimic load conditions that exist when the enable signal is asserted. In another embodiment, a pre-discharge transistor is implemented that charges a terminal of a clocked transistor during certain clock states to mimic load conditions that exist when the enable signal is asserted. Conditional clock gates may also be implemented with multiple enable inputs using these same prnciples.

Abstract: A programmable operational system for managing devices participating in a network including a collection of notices, operation logic that filters the collection of notices based on at least one criteria and that generates at least one operation indicative of a state change of the network, and an automation engine that uses the at least one operation to perform at least one process in response one or more operations. The collection of notices, generated by a plurality of routines, are indicative of the state of hardware, software, and user actions that comprise the network including the state or status of one or more of the devices participating in the network. The operation logic may include an operation engine and one or more operational groups. Each operational group may further include one or more operations, each including a filter and configuration information. The operation logic may further generate at least one job and store the job into memory, where each job references an operation.

Abstract: A fail-over system for memory is provided. The fail-over system for memory includes a virtual channel memory controller providing one or more virtual channel memories in a memory array. A memory fail-over controller coupled to the virtual channel memory controller provides memory fail-over data to the virtual channel memory controller. The virtual channel memory controller allocates one or more of the virtual channel memories to one or more fail-over memory channels in response to the memory fail-over data.