Abstract: A demodulator responsive to a symbol containing analog signal includes a pair of relatively inexpensive analog-to-digital converters for sampling I and Q channels of the signal only once per symbol. A derotator responsive to outputs of the converters and a digital signal representing frequency and phase corrections for an input to the demodulator operates in accordance with a CORDIC function to derive I and Q channel digital signals that are compensated by the corrections. A digital phase shifter responsive to at least one of the digital I and Q signals controls when the input is sampled by the converter.

Abstract: A Radio Frequency (RF)-band tuner stage is combined with a quadrature downconverter stage in a single shielded enclosure as an RF-to-baseband pulse amplitude modulated tuner suitable for receiving RF-band signals from an LNB or the like and converting the signals directly to signals in a desired digital format. The bandwidths within the two stages are optimized for digital PAM demodulation, such as PSK or QAM, and certain functions are shared, such as automatic gain control and carrier tracking information. Electronically switchable attenuators and voltage-variable gain controlled amplifiers, in connection with a low-phase-noise local oscillator employing a microstrip resonator, provide for over 70 dB of dynamic range. The IF frequency and bandwidth are selected so that voltage-variable tunable bandpass filters of conventional design may be used to obtain over 40 dB of radio frequency image rejection necessary for reception of PAM signals.

Abstract: A clock is phase shifted by an amount controlled by the value of a control signal by establishing at least several discrete delay times to be imposed on the clock. The control signal value controls selection of the imposed discrete delay time. An analog-to-digital converter of a phase locked loop responds to intelligence representing variable phase bits and the selected phase shifted clock to control the signal value. The selected replica is derived by at least several cascaded substantially equal time delay units. In one embodiment, a multiplexer responds to the clock, and the signal value, which is Gray coded, to control connections from one of the delay units to an output terminal. In another embodiment, the number of cascaded delay units interposed between the clock and an output terminal is controlled by the signal value.

Abstract: Digital data are communicated from a transmitter to a terrestrial receiver by encoding the data into first and second 1/2 rate convolutional encoded signals during different periods. During the different periods, the convolutional signals are encoded into first and second forward error correction convolutional encoded signals having 2/3 and 6/7 punctured codes transmitted to the receiver via a satellite. Power emitted from the satellite during the first period is 3 db lower than that emitted during the second period. An antenna dish having a diameter no greater than about 1 meter is at the receiver responsive to both signals emitted from the satellite. The encoded signals include sequential bits P.sub.1 (0), P.sub.1 (1), etc. and P.sub.2 (0), P.sub.2 (1), etc. At the 2/3 rate, parallel punctured bit streams respectively including sequential bits P.sub.1 (0), P.sub.2 (1), P.sub.2 (2), P.sub.1 (4) and P.sub.2 (0), P.sub.1 (2), P.sub.2 (3), P.sub.2 (4) are derived.

Abstract: An apparatus and method are provided for simplifying a finite field division, including inputs for the initial condition signals a(x), b(x), and p(x), and providing at an output node the signal c(x), where c(x)=a(x)/b(x) without intermediate inverter circuitry for finding 1/b(x). A reference register initialized to b(x), and a divider register initialized to a(x). Both registers are manipulated in parallel by a logic circuit which responds to the contents of the reference register, converting its contents to 1.Claim By applying the same manipulations to the divider register, its contents are converted from a(x) to a(x)/b(x).One embodiment of a finite field divider according to the present invention is used to provide a single finite field division of a single set of values a(x), b(x) and p(x). Another embodiment processes continuous streams of a(x), b(x) and p(x) values, to provide a continuous stream of c(x) values delayed by a calculation time.

Abstract: L-band tuner stage is combined with a quadrature downconverter stage in a single shielded enclosure as an L-band-to-baseband PSK tuner suitable for receiving L-band signals from an LNB and converting the signals directly to signals in a desired digital format. The bandwidths within the two stages are optimized for digital PSK demodulation, and certain functions are shared, such as automatic gain control and carrier tracking information. Electronically switchable attenuators and voltage-variable gain controlled amplifiers, in connection with a low-phase-noise local oscillator employing a microstrip resonator, provide for over 70 dB of dynamic range. The IF frequency and bandwidth are selected so that voltage-variable tunable bandpass filters of conventional design may be used to obtain over 40 dB of radio frequency (RF) image rejection necessary for reception of PSK signals.

Abstract: Digital data is processed by quantizing the data to produce samples, each with a most significant bits and least significant bits with the least significant bits representing reliabilities, generating a parities from the most significant bits of the samples, generating weight functions corresponding to the parities on the basis of the number of times a reliability measure occurs, and producing a corrected stream of data with the weight functions and the corresponding parities.

Abstract: A finite field parallel multiplier in GF(q.sup.m) including a router for directing 2m-1 components in m groups of m single-component signal lines towards m computing circuits for performing multiply and add modulo-q. The router guides m components from a first finite field element along with an additional m-1 components generated from linear combinations of the m components of the first finite field element. Each of the computing circuits receives all of the components from the second finite field element and m components provided by one set of signal lines through the router. Each computing circuit generates a single component for the resultant finite field element. These resulting components may be input through a basis change circuit to obtain a result in the desired basis.

Abstract: A system for data communication between ground stations using an orbiting satellite as a relay includes a technique for avoiding the loss of signals from the satellite during periods of heavy precipitation. Data is communicated from an orbiting satellite to a plurality of earth stations on a single transmission frequency. The data is communicated on two separate transmission channels on that one frequency by using orthogonal channels of a coherent phase quadrature transmission system. The overall data rate on one of the two transmission channels is much lower than the overall data rate on the other of the two channels. The data on the lower data rate channel is less likely to be affected by heavy precipitation occurring in the line of sight between the satellite and the ground station, and the lower data rate channel is thus used to communicate data to a ground station located in an area of heavy precipitation.