Abstract: The process provides first for the accomplishment of low-doping body regions at the sides and under a gate region and then the accomplishment of high-doping body regions inside said low-doping body regions and self-aligned with said gate region. There is thus obtained an MOS power transistor with vertical current flow which has high-doping body regions self-aligned with said gate region and with a reduced junction depth.
Type:
Grant
Filed:
August 5, 1994
Date of Patent:
July 25, 2000
Assignees:
Consorzio per la Ricerca Sulle Microelettronica nel Mezzogiorno, STMicroelectronics, s.r.l.