Patents Assigned to Contour Semiconductor, Inc.
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Patent number: 8035416Abstract: The present invention relates to electronic driver circuits, and more particularly, to low power electronic driver circuits having low manufacturing costs. The present invention is a circuit design that utilizes two transistor types that can be manufactured together thereby reducing the number of processing steps and masks and resulting in lower cost.Type: GrantFiled: June 30, 2010Date of Patent: October 11, 2011Assignee: Contour Semiconductor, Inc.Inventor: Daniel R. Shepard
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Patent number: 8000129Abstract: Embodiments of the present invention include systems and methods for three-terminal field-emitter triode devices, and memory arrays utilizing the same. In other embodiments, the field-emitter devices include a volume-change material, capable of changing a measurable electrical property of the devices, and/or three-dimensional memory arrays of the same.Type: GrantFiled: December 19, 2008Date of Patent: August 16, 2011Assignee: Contour Semiconductor, Inc.Inventor: Daniel R. Shepard
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Patent number: 7933133Abstract: A high-density memory device is fabricated three-dimensionally in layers. To keep points of failure low, address decoding circuits are included within each layer so that, in addition to power and data lines, only the address signal lines need be interconnected between the layers.Type: GrantFiled: November 5, 2008Date of Patent: April 26, 2011Assignee: Contour Semiconductor, Inc.Inventors: Daniel R. Shepard, Thomas A. Langdo, Arthur J. Pitera
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Patent number: 7916530Abstract: In various embodiments, an addressable storage matrix includes a first plurality of intersection points, at least some of which are bridged by two-terminal non-linear elements that exhibit a threshold below which current flow is significantly lower than if the threshold is exceeded, as well as, disposed at each intersection point bridged by a non-linear element, a programmable material in series with the non-linear element and determining a bit state for the corresponding intersection point.Type: GrantFiled: December 8, 2009Date of Patent: March 29, 2011Assignee: Contour Semiconductor, Inc.Inventor: Daniel R. Shepard
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Publication number: 20110019455Abstract: A high density memory device is fabricated three dimensionally in layers. To keep points of failure low, address decoding circuits are included within each layer so that, in addition to power and data lines, only the address signal lines need be interconnected between the layers.Type: ApplicationFiled: October 5, 2010Publication date: January 27, 2011Applicant: Contour Semiconductor, Inc.Inventor: Daniel R. Shepard
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Patent number: 7826244Abstract: A high density memory device is fabricated three dimensionally in layers. To keep points of failure low, address decoding circuits are included within each layer so that, in addition to power and data lines, only the address signal lines need be interconnected between the layers.Type: GrantFiled: July 20, 2007Date of Patent: November 2, 2010Assignee: Contour Semiconductor, Inc.Inventor: Daniel R. Shepard
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Patent number: 7813157Abstract: A high-speed, low-power memory device comprises an array of non-linear conductors wherein the storage, address decoding, and output detection are all accomplished with diodes or other non-linear conductors. In various embodiments, the row and column resistors are switchable between a high resistance when connected to a row or column that is non-selected, and a low resistance when connected to the selected row and column.Type: GrantFiled: October 29, 2007Date of Patent: October 12, 2010Assignee: Contour Semiconductor, Inc.Inventor: Daniel R. Shepard
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Publication number: 20100149865Abstract: One of the simplest forms of data storage devices is the diode array storage device. However, a problem with diode array storage devices is that as the size of the array increases, the number of non-addressed diodes connected between a given selected row or column of the array and the non-addressed columns or rows of the array, respectively, also becomes very large. While the leakage current through any one non-addressed diode on the selected row or column will have little impact on the operation of the device, the cumulative leakage through multiple thousands of non-addressed diodes can become significant. This aggregate leakage current can become great enough that the output voltage can be shifted such that the threshold for distinguishing between a one state and a zero state of the addressed diode location can become obscured and can result in a misreading of the addressed diode location. The present invention is a means to manage the leakage currents in a diode array storage device.Type: ApplicationFiled: December 8, 2009Publication date: June 17, 2010Applicant: Contour Semiconductor, Inc.Inventor: Daniel R. Shepard
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Patent number: 7682981Abstract: The present invention is a method of applying a topographical surface to a part such as a substrate without the need for low temperature softening of that part while retaining high aspect ratios and densely packed features in that topography. A substrate, selected for its ability to be processed at a given desired temperature, has a layer of material applied to its surface. This layer is selected, among other reasons, for its ability to be molded. Typically, it is expected that the substrate will be able to withstand the higher temperatures of semiconductor post-processing whereas the applied layer will be moldable at low temperatures. This combination enables low cost embossing of a topography into this surface layer. The present invention comprises means to transfer this topography from the low temperature material into the higher temperature substrate.Type: GrantFiled: January 27, 2006Date of Patent: March 23, 2010Assignee: Contour Semiconductor, Inc.Inventor: Daniel Robert Shepard
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Patent number: 7667996Abstract: The scale of the devices in a diode array storage device, and their cost, are reduced by changing the semiconductor based diodes in the storage array to cold cathode, field emitter based devices. The field emitters and a field emitter array may be fabricated utilizing a topography-based lithographic technique.Type: GrantFiled: February 15, 2007Date of Patent: February 23, 2010Assignee: Contour Semiconductor, Inc.Inventor: Daniel R. Shepard
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Patent number: 7652916Abstract: One of the simplest forms of data storage devices is the diode array storage device. However, a problem with diode array storage devices is that as the size of the array increases, the number of non-addressed diodes connected between a given selected row or column of the array and the non-addressed columns or rows of the array, respectively, also becomes very large. While the leakage current through any one non-addressed diode on the selected row or column will have little impact on the operation of the device, the cumulative leakage through multiple thousands of non-addressed diodes can become significant. This aggregate leakage current can become great enough that the output voltage can be shifted such that the threshold for distinguishing between a one state and a zero state of the addressed diode location can become obscured and can result in a misreading of the addressed diode location. The present invention is a means to manage the leakage currents in a diode array storage device.Type: GrantFiled: April 22, 2008Date of Patent: January 26, 2010Assignee: Contour Semiconductor, Inc.Inventor: Daniel R. Shepard
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Patent number: 7593246Abstract: A high density memory device is fabricated three dimensionally in layers. To keep points of failure low, address decoding circuits are included within each layer so that, in addition to power and data lines, only the address signal lines need be interconnected between the layers.Type: GrantFiled: July 20, 2007Date of Patent: September 22, 2009Assignee: Contour Semiconductor, Inc.Inventor: Daniel R. Shepard
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Patent number: 7593256Abstract: Methods and apparatus for differentially measuring the bit state of a particular element in an array of passive nonlinear elements against the output of a reference generator. The reference generator may be, for example, a dummy row circuit, a dummy column circuit, or both a dummy row circuit and a dummy column circuit.Type: GrantFiled: March 28, 2007Date of Patent: September 22, 2009Assignee: Contour Semiconductor, Inc.Inventor: Eric Nestler
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Patent number: 7548453Abstract: Methods and apparatus for providing an array of passive nonlinear elements having an interface circuit that isolates the array from loading effects from external connections to the array. In one embodiment, a capacitive switching circuit is used to electrically isolate the elements in the array from the external load.Type: GrantFiled: March 28, 2007Date of Patent: June 16, 2009Assignee: Contour Semiconductor, Inc.Inventor: Eric Nestler
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Patent number: 7548454Abstract: Methods and apparatus for measuring the bit state of a particular element in an array of passive nonlinear elements that are insensitive to loading effects from external connections to the array. In one embodiment, a switching element is used to electrically isolate the elements in the array from the external load.Type: GrantFiled: March 28, 2007Date of Patent: June 16, 2009Assignee: Contour Semiconductor, Inc.Inventor: Eric Nestler
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Patent number: 7507663Abstract: Fabrication of microelectronic devices is accomplished using a substrate having a recessed pattern. In one approach, a master form is used to replicate a substrate having a pit pattern. In another approach, the substrate is produced by etching. A series of stacked layers having desired electrical characteristics is applied to the substrate and planarized in a manner that creates electrical devices and connections therebetween. The microelectronic devices can include a series of row and columns and are used to store data at their intersection.Type: GrantFiled: January 19, 2007Date of Patent: March 24, 2009Assignee: Contour Semiconductor, Inc.Inventor: Daniel R. Shepard
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Patent number: 7460384Abstract: A high density memory device is fabricated three dimensionally in layers. To keep points of failure low, address decoding circuits are included within each layer so that, in addition to power and data lines, only the address signal lines need be interconnected between the layers.Type: GrantFiled: September 19, 2005Date of Patent: December 2, 2008Assignee: Contour Semiconductor, Inc.Inventor: Daniel Robert Shepard
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Publication number: 20080016414Abstract: A high density memory device is fabricated three dimensionally in layers. To keep points of failure low, address decoding circuits are included within each layer so that, in addition to power and data lines, only the address signal lines need be interconnected between the layers.Type: ApplicationFiled: July 20, 2007Publication date: January 17, 2008Applicant: Contour Semiconductor, Inc.Inventor: Daniel Shepard
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Patent number: RE41733Abstract: A read-only data storage and retrieval device is presented having no moving parts and requiring very low power. Addressing can be accomplished sequentially where the address increments automatically or can be accomplished randomly. High density storage is achieved through the use of a highly symmetric diode matrix that is addressed in both coordinate directions; its symmetry makes the Dual-addressed Rectifier Storage (DRS) Array very scaleable scalable, particularly when made as an integrated circuit. For even greater storage flexibility, multiple digital rectifier storage arrays can be incorporated into the device, one or more of which can be made removable and interchangeable.Type: GrantFiled: March 29, 2001Date of Patent: September 21, 2010Assignee: Contour Semiconductor, Inc.Inventor: Daniel R. Shepard
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Patent number: RE42310Abstract: A read-only data storage and retrieval device is presented having no moving parts and requiring very low power. Addressing can be accomplished sequentially where the address increments automatically or can be accomplished randomly. High density storage is achieved through the use of a highly symmetric diode matrix that is addressed in both coordinate directions; its symmetry makes the Dual-addressed Rectifier Storage (DRS) Array very scaleable, particularly when made as an integrated circuit. For even greater storage flexibility, multiple digital rectifier storage arrays can be incorporated into the device, one or more of which can be made removable and interchangeable.Type: GrantFiled: July 19, 2007Date of Patent: April 26, 2011Assignee: Contour Semiconductor, Inc.Inventor: Daniel R. Shepard