Abstract: A cache-coherent, multiple-bus, multiprocessing system and method interconnects multiple system buses and an I/O bus to a shared main memory and efficiently maintains cache coherency while minimizing the impact to latency and total bandwidth within the system. The system provides coherency filters which coordinate bus-to-bus communications in such a way as to maintain cache memory coherency with a small amount of cross-bus traffic. In addition, the system provides a multiported pool of memory cells which interconnect the multiple buses.
Type:
Grant
Filed:
January 12, 1999
Date of Patent:
April 11, 2000
Assignee:
Corollary, Inc.
Inventors:
Pete D. Vogt, George P. White, Stephen S. Chang
Abstract: A cache-coherent, multiple-bus, multiprocessing system and method interconnects multiple system buses and an I/O bus to a shared main memory and efficiently maintains cache coherency while minimizing the impact to latency and total bandwidth within the system. The system provides coherency filters which coordinate bus-to-bus communications in such a way as to maintain cache memory coherency with a small amount of cross-bus traffic. In addition, the system provides a multiported pool of memory cells which interconnect the multiple buses.
Type:
Grant
Filed:
September 16, 1996
Date of Patent:
April 27, 1999
Assignee:
Corollary, Inc.
Inventors:
Pete D. Vogt, George P. White, Stephen S. Chang
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