Abstract: Configurable I/O circuitry having a plurality of configurable input/output elements, each of which connects one of a plurality of bits of a data bus to a corresponding one of the input/output terminals. Multiple clock selects and programmable enable signals can be connected to different interface elements to control activation of the interface element to which it is connected. The activated interface elements make up a virtual port that can be of any arbitrary bit width that is less than or equal to the fixed width of a physical port. This allows virtual ports on the data bus to be constructed that are narrower than the physical ports so that narrower data can be utilized in the port without causing the potential use of any of the data pins to be lost.

Abstract: Disclosed is a Multiply-Accumulate circuit that includes an exponent adder circuit, a mantissa multiplier circuit, a shifter, a full adder, and an accumulator. The product adder circuit receives two operands in a special combined data format which prescribes a mantissa and an exponent for both integer and floating point operands. The exponent adder circuit adds the exponents of the two operands. But if before the addition the exponent adder circuit detects an integer as an operand, it replaces the exponent of the integer by a substitute value in that addition. This substitute value is related to the number of bits of the mantissa of the integer. The mantissa multiplier circuit multiplies the two mantissas of the two operands. The shifter shifts the resultant product of multiplication into a pre-defined fixed point format according to the resultant sum of the addition generated by the exponent adder circuit. The full adder adds this shifted product to the current content of the accumulator.