Abstract: The invention provides a chip frequency modulation method and apparatus of a computing device, a hash board, a computing device and a storage medium. The chip frequency modulation method comprises: setting a plurality of working frequencies for the operational chip and causing the plurality of cores work at the respective working frequencies; analyzing a computing performance indicator of each core at its current working frequency; and modulating the current working frequency of the core up or down according to the computing performance indicator of the core modulating the frequency of a core with high computing performance up and modulating the frequency of a core with low computing performance down. Therefore, the invention can automatically modulate a frequency corresponding to each core according to the actual computing performance of each core in the operational chip of the computing device, thereby maximizing the computing performance of the cores.

Abstract: The invention provides a voltage-following series power supply circuit, comprising a power supply end and a ground end; a power supply module comprising an input end connected to the power supply end, and an output end for providing a power supply to two or more to-be-powered chips, the power supply module and the to-be-powered chips connected in series between the power supply end and the ground end; and at least one auxiliary power supply module for supplying an auxiliary power supply to the to-be-powered chips, wherein a voltage following module is further connected between the power supply end and the auxiliary power supply module for adjusting a voltage of the auxiliary power supply.

Abstract: The invention provides an on-chip passive power supply compensation circuit, and an operational unit, a chip, a hash board and a computing device using the same. The on-chip passive power supply compensation circuit comprises: two or more to-be-powered voltage domains, wherein the to-be-powered voltage domains are connected in series between a power supply and ground; and two or more isolation regions, wherein the to-be-powered voltage domains are formed in the isolation regions, and the isolation regions are configured for isolating the to-be-powered voltage domains; the isolation regions are connected in series between the power supply and the ground, wherein the on-chip passive power supply compensation circuit further comprises power supply compensation units connected between the to-be-powered voltage domains and the isolation regions for providing power supply compensation to the to-be-powered voltage domains.

Abstract: A computational heat dissipation structure includes a circuit board including a plurality of heating components; and a radiator provided corresponding to the circuit board; wherein a space between the adjacent heating components is negatively correlated with heat dissipation efficiency of a region where the adjacent heating components are located. The computing device of the disclosure includes a device housing enclosing an enclosed heat-dissipation air duct, and the computational heat dissipation structure; the computational heat dissipation structure is located in the enclosed heat-dissipation air duct. Since the space between the adjacent heating components of the disclosure is negatively correlated with the heat dissipation efficiency of the region where the adjacent heating components are located, i.e.

Abstract: The invention provides a full swing voltage conversion circuit. The full swing voltage conversion circuit comprises: an input terminal for inputting a first level signal; an output terminal for outputting a second level signal; a differential input unit for inverting the first level signal of the input terminal, and outputting a differential input signal; a conversion unit; and an output driving unit; wherein the full swing voltage conversion circuit further comprises an auxiliary pull-down unit between the input terminal and the conversion unit for receiving a feedback to improve capability of the conversion unit in recognizing the differential input signal, such that the full swing voltage conversion circuit of the invention can convert from inputting a low voltage to outputting a high voltage.

Abstract: A child balance bike includes a bike body and a coat. The bike body includes a frame, a stem and wheels. The coat includes a main coat body and a head body, wherein the main coat body is provided with lower ends corresponding to legs of an animal, and an inside of the lower ends is provided with an end pocket and a locking portion. The main coat body and the head body are connected as a whole behind the stem, a portion of the coat behind the stem is a filling housing segment through which the head body and the main coat body penetrates and filled with a filler, and the head body is hung on the stem through the filling housing segment filled with the filler. The present invention has a simple structure and convenient operation for connecting.

Abstract: A building and demolition game apparatus includes a base, a plurality of rectangular block elements, a monitoring unit, a game control unit and a force generating unit. The base has an assembly platform located on an upside of the base. The rectangular block elements layered to form a tower, which is stood on the assembly platform. The tower has upper and lower layers held by frictional coupling between the layers. The tower height increases during game play by removing block elements from one or more lower layers to build up successive upper layers upon the assembly platform. The monitoring unit is disposed in the base to obtain at least two boundary conditions by continuously monitoring. The game control unit is disposed in the base to generate a control signal according to a predetermined threshold and the at least two boundary conditions. The force generating unit is disposed in the base and under the assembly platform.

Abstract: The invention provides a dynamic D flip-flop, and a data operation unit, a chip, a hash board and a computing device using the same. The dynamic D flip-flop comprises: an input terminal, an output terminal and at least one clock signal terminal; a latch unit for latching data of the input terminal and inversely transmitting the data under control of a clock signal; and an output driving unit for inverting and outputting the data received from the latch unit; wherein the latch unit outputs in high level, low level and high impedance states by means of a single element under control of a clock signal. Therefore, the invention can effectively reduce chip area, power consumption, and logic delay.

Abstract: A data conversion unit that converts all or part of first data including secret target information and a part including the secret target information, into second data for reading or viewing; a masking processing unit that performs masking processing on the second data, thereby generating masking data; a storage unit that stores the masking data; and an output unit that outputs the masking data stored in the storage unit.

Abstract: The invention provides a dynamic D flip-flop, and a data operation unit, a chip, a hash board and a computing device using the same. The dynamic D flip-flop comprises: an input terminal, an output terminal and at least one clock signal terminal; a first latch unit for transmitting data of the input terminal and latching the data under control of a clock signal; a second latch unit for latching data of the output terminal and inversely transmitting the data latched by the first latch unit under control of a clock signal; and an output driving unit for inverting and outputting the data received from the second latch unit; wherein the second latch unit outputs in high level, low level and high impedance states by means of a single element under control of a clock signal. Therefore, the invention can effectively reduce chip area, power consumption, and logic delay.

Abstract: A muscle training apparatus capable of generating a force is disclosed. The muscle training apparatus includes a second support shell, a force-generating unit and an elastic covering unit. The second support shell is spherical and has a second containing space. The force-generating unit is disposed and fixed in the second containing space of the second supporting shell for generating a force. The elastic covering unit covers the second support shell to have a soft surface. The muscle training device can generate a force in a specific direction and intensity by the force-generating unit.

Abstract: A data conversion unit that converts all or part of first data including secret target information and a part including the secret target information, into second data for reading or viewing; a masking processing unit that performs masking processing on the second data, thereby generating masking data; a storage unit that stores the masking data; and an output unit that outputs the masking data stored in the storage unit.

Abstract: A muscle training apparatus with muscle strength detecting function includes a first supporting shell, a plurality of membrane pressure-sensing units, an arithmetic processing unit and an elastic covering unit. The first support shell is spherical and has a first outer surface and a first containing space. The membrane pressure-sensing unit is disposed on the first outer surface of the first support shell. The arithmetic processing unit is disposed in the first containing space and electrically connected to the membrane pressure-sensing unit. The elastic covering unit covers the first support shell.

Abstract: A communications system includes a device connected to information terminals to enable a plurality of information terminals, mutually exchange data via a global network and enable highly confidential mutual communications between the information terminals included. The communications device includes a unit storing user authentication information for performing user authentication via the connected information terminal and pre-storing a device authentication listing pieces of device information in authentication of each communications device with regard to all the communications devices in the same group, the device authentication list being pre-stored in a state where the device authentication list is inaccessible from the user.

Abstract: A communications system includes a device connected to information terminals to enable a plurality of information terminals, mutually exchange data via a global network and enable highly confidential mutual communications between the information terminals included. The communications device includes a unit storing user authentication information for performing user authentication via the connected information terminal and pre-storing a device authentication listing pieces of device information in authentication of each communications device with regard to all the communications devices in the same group, the device authentication list being pre-stored in a state where the device authentication list is inaccessible from the user.