Abstract: A bi-convex solid immersion lens is disclosed, having a top and bottom convex surfaces. The radius of curvature of the bottom surface is larger than that of the top surface. A conical sloped side-wall connects the top and bottom surface.

Abstract: PICA probe system apparatus is described, including apparatus for calibrating an event timer having a coarse measurement capability in which time intervals defined by clock boundaries are counted and a fine measurement capability in which time between boundaries is interpolated using a voltage ramp.

Abstract: A system for probe-less non-invasive detection of electrical signals from integrated circuit devices is disclosed. The system includes an illumination source, collection optics, imaging optics, and a photon sensor. In a navigation mode, the light source is activated and the imaging optics is used to identify the target area on the chip and appropriately position the collection optics. Once the collection optics is appropriately positioned, the light source is deactivated and the photon sensor is used to detect photons emitted from the chip. No mention of cooling (active device measurement capability) and advanced optics to detect the features (SIL).

Abstract: A test apparatus including a means for sending a first test pattern to a device under test (DUT), where the first test pattern is a part of a planned sequence of tests, and further including a means for evaluating the test results received from the DUT, and a method of testing are described. The test results may include anomalous data indicative of a defect in the DUT. If so, a second test pattern that is not part of the planned sequence of tests is selected. The second test pattern is selected based on a diagnosis of the anomalous data by the test apparatus.

Abstract: A test circuit is fabricated in the device layer of the wafer. Metal contact is made between the test circuit and at least one metal layer, e.g., M2. The normal metal line fabrication process, e.g. Damascene process, is performed to fabricate contacts and pattern the trenches of the metal lines. After the metal layer of the contact layer, e.g., M2 is provided over the wafer to cover the trenches, the metal layer is contacted by the probe to send test signals to the test circuit. The electrical response characteristics can then be observed. After the testing, CMP of the metal layer is performed in the normal process of patterning the trenches, thereby removing any potential contamination introduced during the electrical testing.

Abstract: A self-calibrating strobe signal generator for a BIST circuit responds to an edge of an input strobe signal by generating corresponding edges of first and second strobe signals separated in time by a target delay specified by input data. The strobe signal generator includes a multiplexer, a delay circuit and a controller. The multiplexer normally provides the input strobe signal as a multiplexer output signal to the delay circuit which generates edges in each of the first and second strobe signals in response to each edge in the multiplexer output signal with a programmable delay between corresponding first and second strobe signal edges.

Abstract: A test apparatus implements a method for testing electronic devices that exhibit non-deterministic behavior. The test apparatus includes a high-speed buffer queue for storing data packets. The data packets arrive at one end of the queue and, as they exit at the other end, are compared against expect data packets stored in memory. If the data packet exiting the buffer queue corresponds to response signals generated by the device under test during a non-deterministic (e.g., idle) state, the expect data packet is not retrieved from memory and the comparison is not made.

Abstract: The present invention relates to test systems for testing integrated circuit devices and to calibration associated systems and methods. One embodiment of the invention provides a method for providing formatted levels for use in a test system. The method includes: providing on a single CMOS IC, a timing generation circuit operative to provide timing information signals; and a formatter in communication with the timing generation circuit.

Abstract: An apparatus for providing modulation mapping is disclosed. The apparatus includes a laser source, a motion mechanism providing relative motion between the laser beam and the DUT, signal collection mechanism, which include a photodetector and appropriate electronics for collecting modulated laser light reflected from the DUT, and a display mechanism for displaying a spatial modulation map which consists of the collected modulated laser light over a selected time period and a selected area of the IC.

Abstract: A system for probing a DUT is disclosed, the system having a pulsed laser source, a CW laser source, beam optics designed to point a reference beam and a probing beam at the same location on the DUT, optical detectors for detecting the reflected reference and probing beams, and a collection electronics. The beam optics is a common-path polarization differential probing (PDP) optics. The common-path PDP optics divides the incident laser beam into two beams of orthogonal polarization - one beam simulating a reference beam while the other simulating a probing beam. Both reference and probing beams are pointed to the same location on the DUT. Due to the intrinsic asymmetry of a CMOS transistor, the interaction of the reference and probing beams with the DUT result in different phase modulation in each beam. This difference can be investigated to study the response of the DUT to the stimulus signal.

Abstract: A test apparatus has multiple instruments that are synchronized with respect to one another so that a trigger signal may be generated in response to events occurring at different instruments. The events may correspond to events defined within a test program or events detected at a device under test. A partial trigger signal is generated by each of the different instruments, and the partial trigger signals are used in generating the trigger signal. Different offset delays are applied to the partial trigger signals so that the partial trigger signals generated by the different instruments are synchronized with respect to each other.

Abstract: A jitter generator produces a jittery test signal for use in performing a jitter test on an integrated circuit (IC) device under test (DUT). The jitter generator includes a programmable delay circuit for delaying a non-jittery input signal with a varying delay controlled by input digital delay control data to produce the test signal. A pattern generator supplies a sequence of delay control data to the programmable delay circuit causing it to produce a desired jitter pattern in the test signal. During a calibration process, a measurement unit feeds the test signal back to the input of the programmable delay circuit, causing the test signal to oscillate with a period proportional to the delay through the delay circuit. The measurement unit then measures the period of the test signal for various values of delay control data and reports measurement results.

Abstract: An apparatus for testing an integrated circuit, the apparatus including a sequence control logic unit having an output channel connectable to a device under test, and a memory to store at least two types of data sets, each data set being used by the sequence control logic unit to determine a test pattern to output on the output channel.

Abstract: A test head for a semiconductor integrated circuit tester includes a main support structure defining a device interface board location, and a contact support frame that is displaceable relative to the main support structure for engaging a device interface board at the device interface board location.

Abstract: A system for probing a DUT is provided, the system comprising a tunable or CW laser source, a modulator for modulating the output of the laser source, a beam optics designed to point a probing beam at a designated location on the DUT, optical detector for detecting the reflected beam, and collection and signal processing electronics. The system deciphers perturbations in the reflected beam by detecting beat frequency between operation frequency of the DUT and frequency of the modulation. In an alternative embodiment, the laser is CW and the modulation is applied to the optical detector.

Abstract: Testing an integrated circuit (IC) device, for example, an IC that includes an embedded memory, may involve specifying one or more test parameters including at least one of a pipeline depth data (e.g., latency delay information) and a data width data (e.g. corresponding to a data width of an embedded memory), generating a test sequence by associating test parameters with a test pattern, and applying the generated test sequence to the integrated circuit device. A test system for testing ICs having embedded memories may include multiple test patterns and multiple data structures, each data structure defining one or more test parameters including at least one of a pipeline depth and a data width, an algorithmic pattern generator, and software for controlling the algorithmic pattern generator to generate a test sequence by associating a specified data structure with a specified test pattern.

Abstract: A method and apparatus for defining a circuit operation, such as a charged particle beam operation to perform a circuit edit and define a probe point. Circuit operation definition is performed in a front-end environment with access to integrated circuit computer aided design tools providing logic level and layout level information concerning the integrated circuit. The front-end environment incorporates circuit operation optimization methods to identify optimal locations for a circuit operation. A back-end environment, such as a charged particle tool computing platform, is adapted to receive one or more files, which may include a truncated layout file with circuit operation location information, for use in further defining a circuit operation and/or performing the circuit operation.

Abstract: A collection optics arrangement integrating an objective lens and a solid immersion lens. An objective lens housing has an objective lens mounted inside. A solid immersion lens (SIL) housing is slidably mounted onto said objective lens housing, and a solid immersion lens is mounted onto the SIL housing. A spring imparts resilient force resisting the sliding of the solid immersion lens housing with respect to the objective lens housing.

Abstract: The backside navigation method of the present invention includes milling a fiducial opening through the substrate of an integrated circuit. The milling process is stopped when the fiducial opening reaches the bottom of a trench isolation structure. The trench isolation structure delineated by the fiducial opening may be imaged and registered to a computer aided design layout image to achieve sub-micron navigation resolution.

Abstract: A charged particle guide adapted to be coupled with a charged particle detector, such as a secondary electron detector. The charged particle guide, in one example, comprising two wires extending from the charged particle detector toward a source of charged particles, such as secondary electrons emitted from an IC upon application of a focused ion beam. Upon application of a bias voltage, the charged particle guide introduces a collecting electric field that attracts charged particles and directs the charged particles to the charged particles detector.