Abstract: In an error trapping decoder in which a received codeword is shifted through a re-encoder shift register to produce a set of r syndrome characters and in which the encoder shift register is then isolated and its contents shifted until a number of consecutive zero virtual check characters is produced therein, the capacity to trap long error bursts is enhanced by increasing the size of the code and by demanding that the minimum number of consecutive zero virtual check characters be only sufficient to ensure an acceptably low probability that one or more of the zero-value virtual check characters is a false indication. Such a decoder may be used to determine the location of an error burst in a received block of interleaved codewords as long as at least one of the codewords in the block produces the minimum number of consecutive zero-value virtual check characters after a requisite number of shifts of the encoder.

Abstract: Multiplication of two mq-bit bytes (in GF2.sup.mq) is reduced modulus an irreducible polynomial in GF2.sup.m of degree q to multiplication among two sets of q m bit bytes (in GF2.sup.m) in order to simplify hardware and reduce costs, by distributing the computation among a small number of programmable read only memories (PROMs) and adders.

Abstract: By translating in accordance with a predetermined permutation the virtual check locations of a virtual message re-encoder, plural erroneous symbols (up to a certain limit) occurring in any pattern in a received codeword may be trapped simultaneously in virtual check locations. By simply adding to them the corresponding virtual check symbols computed by the virtual message re-encoder, the correct codeword is easily obtained. In one embodiment of the invention, any pattern of two erroneous symbols in a codeword of length n may be trapped in this manner by defining the predetermined permutation in accordance with a modulus n cyclic difference set. In this embodiment, for an RS(31, 25) code, the cyclic difference set (0, 4, 10, 23, 24, 26) may be used as the predetermined permutation.

Abstract: A block of helically interleaved codewords is received in a de-interleaving array. A succession of codewords obtained from the de-interleaving array are decoded in a process in which each error pattern in a given codeword position provides a prediction of the presence or absence of an erasure in the adjacent codeword position of the next codeword. This prediction is obtained by addressing a look-up table with the error pattern. In one embodiment of the invention, the erasure prediction is computed recursively from previous erasure predictions using individual skepticism factors and forgetting factors for each codeword symbol position.

Abstract: A systematic systolic array of R Cauchy cells receives a message stream of K symbols, systolically computes R check symbols therefrom and appends them to the end of the meassage stream to form a codeword of N=K+R symbols. The Cauchy cells operate independently, there being no feedback as is usually required, so that only adjacent cells need operate synchronously, a clock signal being systolically passed from cell to cell and the systolic array as a whole being asynchronous. As a result, the encoder may operate at much higher data rates and is easily reconfigurable in real time to adjust for any changes in the number of message symbols (K) or the number of check symbols (R).

Abstract: An error detection and correction processor computes in real time successive approximations to a Galois field error locator polynomial and a Galois field error evaluator polynomial from the remainder or syndrome polynomial of a received block of data by executing successive iterations of a recursive algorithm. The processor stores each coefficient of the polynomials in an individually addressable memory location. During each iteration, the processor operates on successive ones of the coefficients of each polynomial in successive memory access cycles to compute a new version of the coefficient which replaces the old one in memory.

Abstract: The n symbols of a codeword of length n are transmitted on n separate channels or frequencies simultaneously. A receiver includes n equalizers that are adapted to receive information from respective ones of the n channels. The outputs of the n equalizers are applied to n inputs of an error correcting decoder which produces the original version of the transmitted codeword. The n equalizers include n feedforward and n feedback transversal filters whose taps are updated by n tap update processors in accordance with a Kalman algorithm, or the like, once each codeword time. The feedforward registers contain successively received signal samples of each of the n channels while the n decision feedback registers contain successively corrected symbols generated at each of the n decoder outputs.

Abstract: In a Reed-Solomon Decoder, each byte of a received codeword is matched to the closest resembling one of a set of allowed symbols and assigned a certain reliability, reflecting the degree of resemblance. The symbols thus matched are arranged in descending order to reliability to form a virtual codeword, the first K symbols being virtual message bytes and the remaining r symbols being virtual check bytes. The virtual codeword is then decoded using an algorithm which produces a series of iterative approximations to the transmitted codeword. The approximation most closely resembling the received codeword is selected as the corrected codeword.

Abstract: A digital phase lock loop includes a variable precision modular counter which adjusts the output phase by changing the counter modulus by an amount proportional to the current modulus of the counter to preserve the effectiveness of each such change over a wide range of moduli, thereby increasing the effective bandwidth of the digital phase lock loop. The digital phase lock loop is characterized by an exponential duty cycle phase adjustment which avoids spurious oscillations due to either overdamping or resonance, thus increasing loop stability.

Abstract: Plural n-symbol codewords are helically interleaved and transmitted in a stream. A receiver views the transmitted stream through n time windows, each time window having a length accommodating the longest anticipated decorrelation time of the channel. Individual equalizers process the data in individual windows. The n windows simultaneously furnish the n symbols of each codeword to an error correction decoder. The n equalizers respond to feedback in which the output of the decoder is substituted in place of undecoded symbols from the n windows whenever available.

Abstract: In a multi-channel apparatus, a first plurality of N channels support user data and associated error correction and a second plurality of channels each contain a unique p-bit symbol followed by N consecutive M-bit samples of each of the N data channels. The receiver or retriever apparatus regenerates a system clock from all channels and examines the respective bit streams to score each bit phase as a match or a non-match of the sample in the synch channel with each M bit sample of the respective N data streams, and for each such N channels a counter corresponding to the then current phase is incremented or decremented. Relative skew for the N channels is derived from the addresses of the first counter to overflow for each of the N channels.

Abstract: Error correction for polynomial block codes is achieved without prior evaluation of power sum symmetric functions. The received word R (z) is reduced mod G (z), the generator of the code and a function F (z) of error locator polynomial W(z), errata values Y and code dependent functions f(x.sub.i) of the error positions x.sub.i given by ##EQU1## is decomposed into a rational polynomial function N (z)/W (z) for which deg (N (z) )<deg ( W (z) )<number of correctable errors. W (z) is the error locator polynomial, the roots of which are the errata locations X and Y, the correction to the received character is obtained from ##EQU2## evaluated at X.sub.i using non-erased check symbols of R (z). Correction is carried out in a crossbar switch structure which recalls a stored copy of R (z) and corrects bits as specified by (X.sub.i, Y.sub.i).

Abstract: To each bit time of a data block, there is associated a counter which is incremented or decremented in accord with the congruence or non-congruence of the c bit sequence associated with the respective counter (for example, the first bit of the c bit sequence). The counters are initialized to an optimum non-zero value and after receiving a number of blocks of data, each containing one sync symbol, the synchronization is determined from the relative content of the counters.

Abstract: An improved method and apparatus for interleaving block codes exploits helical symmetry whereby correspondingly positioned code symbols of code words of length n interleaved to depth i, i<n, are separated on the channel by .alpha.i+.beta. symbol intervals where 1+.gamma..gtoreq.i is averaged over the i correspondingly positioned symbols and .alpha.and .vertline..beta..vertline. are integers >1. The requirement for synchrony is reduced to a period counted modulo n instead of mod (n.times.i). For the case i=n-1, the total interleaving delay is reduced to 2(n-1)n and phase dependence of burst error onset is minimized. The performance of the de-interleaver is enhanced through a pseudo fade detector implemented by creating erasures prior to decoding, at certain positions for codewords subsequent to confirmed error. Synchronization of interleaver and de-interleaver is accomplished in apparatus which inspects all c contiguous bit patterns corresponding to a c bit synch symbol.

Abstract: An encoder for Reed Solomon codes employs structure for producing interleaved code wherein redundancy bits are realized by a bit serial multiplicative procedure. Operations are accomplished with respect to the dual basis to the conventional polynomial representational basis as coefficients of successive powers of an element of a finite field. Code bits are generated and interleaved by a feedback shift register constructed from standard RAM chips. The structure is simplified by selection of a generator polynomial from a class which exhibits symmetry whereby the number of independent coefficients for representing the generator polynomial is halved.

Abstract: Errors are corrected in a cyclic encoded data stream, consisting of sequential groups of data bits and check bits, by means of a novel digital computer. The computer employs a stored program and is organized into three distinct substructures, each having an independent internal addressable memory and all capable of synchronous concurrent operation. An arithmetic unit substructure including a data memory implements finite field arithmetic operations upon received data.The arithmetic unit includes a Galois field manipulative subunit for producing finite field products and sums over the field GF(2.sup.5) from operands selected from three registers which derive data from the memory of the arithmetic unit, another register, or the result of a currently executed Galois field operation. The preferred embodiment is especially suitable for correcting data encoded in the Reed-Solomon (31,15) code.An address generator realizes address modification in the Galois field GF(2.sup.