Patents Assigned to Cypress Semiconductor Corportion
  • Single-wafer process for fabricating a nonvolatile charge trap memory device
    Patent number: 7670963
    Abstract: A method for fabricating a nonvolatile charge trap memory device is described. The method includes first forming a tunnel dielectric layer on a substrate in a first process chamber of a single-wafer cluster tool. A charge-trapping layer is then formed on the tunnel dielectric layer in a second process chamber of the single-wafer cluster tool. A top dielectric layer is then formed on the charge-trapping layer in the second or in a third process chamber of the single-wafer cluster tool.
    Type: Grant
    Filed: September 26, 2007
    Date of Patent: March 2, 2010
    Assignee: Cypress Semiconductor Corportion
    Inventors: Krishnaswamy Ramkumar, Sagy Levy
  • Method and apparatus for configuring signal lines according to idle codes
    Patent number: 7301961
    Abstract: A method and apparatus for configuring signal lines with idle codes is disclosed. According to one embodiment, data transmission system (100) may include encoders (112, 114, 116 and 118) that transmit data over signal line lanes (Lane 0 to Lane n). In an idle state, an encoder (112, 114, 116 and 118) may output one of at least two idle codes (IDLE A and IDLE B). One idle code (IDLE A) may indicate a first lane of a group of lanes. Another idle code (IDLE B) may indicate subsequent lanes of a group of lanes.
    Type: Grant
    Filed: July 31, 2002
    Date of Patent: November 27, 2007
    Assignee: Cypress Semiconductor Corportion
    Inventors: David V. James, Jagadeesan Rajamanickam