Abstract: Systems and methods in which an ultrasonic signal is introduced into an audio signal before the audio signal is amplified by a switching amplifier. The added ultrasonic signal (e.g., a tone at half the amplifier's switching frequency) shifts the signals input to a set of power switches so that they do not switch nearly simultaneously. The ultrasonic signal causes the output current to be well defined to eliminate dead time distortion at low signal levels. Adding the tone ultrasonic signal causes the distortion to shift to an amplitude greater than zero. Signals that exceed this amplitude will experience the distortion, but the distortion will be less noticeable than in lower-amplitude signals. Signals that do not exceed this amplitude will not experience the distortion at all. Adding an ultrasonic signal may also draw energy away from the switch frequency and its harmonics to interference with AM radio reception.

Abstract: A low delay corrector (LDC) unit includes a non-linear function generator and a filter. The nonlinear function generator receives a first signal and outputs a second signal in dependence on the first signal and a transfer function of the nonlinear function generator. The filter is fed in dependence on the second signal output by the nonlinear function generator. The first signal received by the nonlinear function generator is derived in dependence on an input signal provided to an input of the LDC unit and an output of the filter. An output of the LDC unit is derived in dependence on the first signal received by the nonlinear function generator and the second signal output by the nonlinear function generator.

Abstract: Systems and methods for detecting clipping conditions in an audio signal and processing the signal to reduce the clipping conditions. In one embodiment, a system comprises a noise shaper, a modulator, an output stage and other components. A detector detects clipping in the noise shaper and a signal processor processes the audio signal input to the noise shaper based on feedback received from the detector. The signal processor may function to modify the input audio signal in different ways in response to different conditions that are detected by the detector. A filter may be included to filter the output of the detector before being provided to the signal processor. A flag circuit may be coupled between the filter and the signal processor to assert an output signal until the signal processor resets the flag circuit.

Abstract: Systems and methods for synchronizing multiple digital audio controller chips, wherein one of the chips is designated as a master and the other chips are designated as slaves. A common line connects all of the chips and is used to transmit synchronization signals from the master to the slaves. Each of the chips listens for an appropriate signal and, when the signal is detected, all of the chips simultaneously begin operation. In one embodiment, the synchronization signal comprises a transition on the shared line to an active state. The transition is repeated at fixed intervals and maintained in the active state for a fixed period in order to enable the chips to determine whether synchronization is being maintained. The signal may be sampled and/or filtered to improve reliability. The chips may be able to drive the shared line active to indicate that synchronization has been lost.

Abstract: Systems and methods for performance improvements in digital switching amplifiers using a low delay corrector. In one embodiment, a digital pulse width modulation (PWM) amplifier includes a signal processing plant configured to receive and process an input audio signal. The amplifier also includes a low delay corrector configured to receive signals output by the plant. The output of the low delay corrector is added to the input audio signal as feedback. The plant may consist of a modulator and power switch, a noise shaper, or any other type of plant. An analog-to-digital converter (ADC) may be provided to convert the output audio signal to a digital signal. Filtering may be implemented before or after the ADC, and a decimator may be placed after the ADC if it is an oversampling ADC.

Abstract: Systems and methods for improving the stability of feedback and/or feed-forward subsystems in digital amplifiers. One embodiment comprises a digital pulse width modulation (PWM) controller. The controller includes an input for receiving a digital audio input signal and is configured to generate a PWM output signal based on the input signal at an output. The controller also has control inputs for receiving external audio correction signals such as feedback and power supply feed-forward signals. The controller has correction circuitry for processing the received external control signals and modifying the input signal based on these signals. Fault detectors monitor fault conditions at various locations within the correction circuitry, and a protection control unit receives fault signals from the fault detectors and modifies operation of the controller in response to the fault signals.

Abstract: Systems and methods for minimizing performance degradation due to component mismatch in the feedback path of a digital PWM amplifier feedback loop. One embodiment comprises a digital pulse width modulated (PWM) amplifier with feedback. The amplification subsystem receives a digital audio signal and produces an analog output signal. The feedback loop produces a feedback signal based on the filtered analog output signal and modifies the digital audio signal based on the feedback signal. The feedback loop includes a filter configured to filter the analog output signal and correction circuitry configured to correct component mismatch errors introduced by the filter. In one embodiment, the correction circuitry receives a measurement of a power supply voltage, multiplies the measured voltage by a gain and adds the scaled measurement to the feedback signal to correct for the component mismatch errors.

Abstract: Systems and methods for using multiple rate estimate counters in converting input data streams having variable sample rates to an output sample rate that are used in processing the data streams. In one embodiment, a system includes a clock source, first and second counters coupled to the clock source and configured to count cycles for corresponding data streams, and a data processor coupled to the first and second counters. The data processor is configured to read the number of cycles counted by each of the counters between received frame sync signals and to convert the first data stream to the predetermined output sample rate based on the corresponding number of cycles counted, and to convert the second data stream to the predetermined output sample rate based on the ratio of the numbers of cycles counted in the first and second counters.

Abstract: Systems and methods for transferring data across clock domains in a manner that avoids metastability of the data and is very tolerant of variations in the clock signals of the different clock domains. One embodiment of the invention comprises a mechanism for passing data from a first clock to a second clock domain in a digital pulse width modulated (PWM) amplification system. In this embodiment, parallel data is generated in the process of converting PCM data to PWM data. The parallel data is processed in a clock domain having a first clock rate and is passed to a second clock domain having a clock rate that is twice the rate of the first clock domain. The parallel data is then serialized at the higher clock rate of the second clock domain.

Abstract: Systems and methods for preventing violations of minimum pulse width requirements that may cause damage to PWM amplifiers. One embodiment comprises a digital PWM amplifier that includes shutdown circuitry which is configured to identify blockout intervals during which deassertion of the PWM signals would cause the generation of below-minimum-width pulses in the signals. Each blockout interval may, for example, begin 1 minimum pulse width before and end 1 minimum pulse width after a rising/falling edge the PWM signals. If a shutdown signal is asserted (or deasserted) during one of the blockout intervals, the PWM signals are deasserted (or reasserted) at the end of the blockout interval.

Abstract: Systems and methods for minimizing errors due to component variation in switching amplifiers utilizing power supply feed forward techniques. One embodiment comprises a digital PWM amplifier having an amplification subsystem for receiving a digital audio signal and producing an analog output signal. The amplifier includes a power supply feed-forward path configured to modify the digital audio signal based on a power supply measurement. The feed-forward path includes an analog filter configured to filter the power supply measurement, as well as correction circuitry configured to correct component mismatch errors introduced by the filter. The power supply measurement may be a power supply difference, a power supply common mode, or both. In either case, the power supply measurement is corrected by multiplying the measurement by an appropriately scaled power supply difference.

Abstract: Systems and methods for pulse width modulating waveforms to represent asymmetric signal levels using pulses that are symmetric within their respective switching periods. One embodiment comprises a pulse width modulation system including an asymmetric correction unit and a pair of modulators. The asymmetric correction unit receives samples of an input signal and produces two separate output signals for corresponding modulators. For each sample, the asymmetric correction unit determines whether the signal level of the sample is symmetric or asymmetric. If the signal level of the sample is symmetric, the sample is forwarded to each of the modulators. If the signal level is asymmetric, the asymmetric correction unit increases one modified sample to the next higher symmetric signal level and decreases another modified sample to the next lower symmetric signal level and forwards the modified samples to the modulators.

Abstract: Systems and methods for minimizing delay in a feedback path. In one embodiment, an analog-to-digital feedback path includes an analog-to-digital converter (ADC) configured to receive and digitize an analog signal such as an amplifier output to produce a serial digital output. A serial interface receives and parallelizes the serial digital output to produce a parallel data words that are provided to a processing unit such as a decimator. The processing unit processes the data words to produce a digital feedback signal which can then be used to modify an input signal, such as a digital audio input to the amplifier. A delay minimization subsystem is implemented in the feedback path to monitor a delay between generation of parallel data words by the serial interface and consumption of the parallel data words by the first processing unit. The delay minimization mechanism may be implemented in multiple channels of the feedback path.

Abstract: Systems and methods implemented in a multi-bit digital noise shaper for reducing or eliminating undesirable transient response when the noise shaper exits a clipping state. In one embodiment, the noise shaper includes a quantizer, a filter, and a filter control unit that detects clipping in the quantizer and dynamically adjusts the allowable range of the internal state values of the filter. In one embodiment, a clipping mechanism is provided for each state value within the filter to clip the state value if it exceeds a corresponding clipping level. The clipping level for each state value is lower when the quantizer is clipping, and higher when the quantizer is not clipping. The clipping level for each state value may be transitioned either immediately or gradually from a current level to a target level (which is lower when the quantizer is clipping, and higher when the quantizer is not clipping.

Abstract: Systems and methods for over-current protection in all-digital amplifiers using low-cost current sensing mechanisms. An over-current hard clipping unit receives a digital audio signal, clips the signal according to a clip level, and provides the signal to a modulator. The modulator modulates the signal to produce, e.g., a PWM signal and provides the modulated signal to an output stage which generates an output current to drive a speaker. An over-current sensing unit is compares the output current to a threshold value and generates a binary signal indicating whether the output current exceeds the threshold value. The hard clipping unit receives the binary signal and ramps down the clip level during time periods in which the binary signal indicates that the output current exceeds the threshold. When the binary signal indicates that the output current does not exceed the threshold value, the hard clipping unit ramps up the clip level.

Abstract: Systems and methods for performance improvements in digital switching amplifiers using simulation-based feedback. In one embodiment, a digital pulse width modulation (PWM) amplifier includes a signal processing plant configured to receive and process an input audio signal. The amplifier also includes a simulator configured to model processing of audio signals by the plant. The outputs of the plant and the simulator are provided to a subtractor, the output of which is then added to the input audio signal as feedback. The plant may consist of a modulator and power switch, a noise shaper, or any other type of plant. An analog-to-digital converter (ADC) may be provided to convert the output audio signal to a digital signal for input to the subtractor. Filtering may be implemented before or after the ADC, and a decimator may be placed after the ADC if it is an oversampling ADC.

Abstract: Systems and methods for detecting the impedance of an output load coupled to a digital amplifier and compensating for changes in the response of the amplifier. One embodiment of the invention is implemented in a Class D pulse width modulated (PWM) amplifier. In this embodiment, a digital PCM test signal is generated. This test signal is processed by the amplifier to produce a corresponding analog audio output signal that is used to drive a speaker. A sense resistor placed in series with the speaker is used to generate a test voltage that is compared to a reference voltage. When the test voltage reaches the reference voltage, the current through the sense resistor (hence the speaker) is at a known level, so the value of the digital test signal is noted. The impedance of the speaker is then determined from the test signal value and the speaker current.

Abstract: Systems and methods for converting a digital input data stream from a first sample rate to a second, fixed sample rate using a combination of hardware and software components. In one embodiment, a system includes a rate estimator configured to estimate the sample rate of an input data stream, a phase selection unit configured to select a phase for interpolation of a set of polyphase filter coefficients based on the estimated sample rate, a coefficient interpolator configured to interpolate the filter coefficients based on the selected phase, and a convolution unit configured to convolve the interpolated filter coefficients with samples of the input data stream to produce samples of a re-sampled output data stream. One or more hardware or software components are shared between multiple channels that can process data streams having independently variable sample rates.

Abstract: Systems and methods for controlling amplification of a pair of pulse width modulated signals. In one embodiment, a system comprises an audio amplifier which is configured to receive a pulse code modulated (PCM) input signal, convert this signal to a pulse width modulated (PWM) signal in a controller, and amplify the PWM signal in an output stage. The controller separates the PWM signal into a high-side signal and a low-side signal. The controller incorporates digitally programmable delays into the processing paths for each of the high-side and low-side signals. The high-side and low-side signals are separately provided to the output stage. The separate high-side and low-side signals can be used to individually control (e.g., turn off) the high-side and low-side transistors. Circuitry is included to generate a short low-side pulse when both transistors are turned off in order to drain the gate charge from the high-side transistor.

Abstract: Systems and methods for reducing the noise level in a multi-channel digital audio system by staggering the timing of the pulse-width modulation in the different channels and thereby reducing the magnitude and increasing the frequency characteristics of the generated switching noise. One embodiment comprises a multi-channel digital PWM amplifier in which the timing signals used by each channel's modulator are staggered to evenly space the switching edges of the generated PWM signals. An additional, complementary delay is implemented in each of the channels to equalize the total delay for each channel so that the outputs of the channels are synchronized. The different channels may be implemented on different chips, in which case the chips may be synchronized prior to staggering the signals processed in each of the channels.