Abstract: A battery-backed microprocessor which enters a known state on power-down. This is achieved, even if the microprocessor does not permit a single-cycle reset, by providing clock intercept circuitry on chip. When system power failure is detected, the clock intercept circuitry disconnects the external clock, activates a reset command, and then generates several clock cycles using an internal clock generator after the reset command. As many clock cycles are generated as is needed, with the particular architecture being used, to reach a predetermined state.

Abstract: A low-power SRAM with redundant rows in each of the subarrays. Conventional redundancy logic permits defective rows to be electrically replaced by redundant rows. In addition, power supply disconnect logic permits the V.sub.DD supply voltage line for the bad row to be disconnected.

Abstract: An electronic key integrated circuit which includes three independently addressable partitions of secure memory. Each of these three partitions can function as a separate "subkey." Each of the subkeys is independently password-protected.In addition to the secure subkey memory partitions, the integrated circuit also contains a read/write "scratchpad" memory, which is the same size as each of the subkeys. After data has been written into the scratchpad (and verified if desired), it can be copied, as a block, onto one of the subkey partitions. However, to perform such a block move the password of the target subkey must also be specified.

Abstract: Battery monitor (100) with a transient pull down (172) for backup batteries which is active during power up and prevents the feedthrough charging of low or dead batteries causing a spurious power fail indication.

Abstract: A class of layout patterns for variable resistors and integrated circuits where the resistance is varied by varying a wiping point on a resistor line; contact is not made into the resistor line itself, but instead all contacts are made only to tabs which extend out from the resistor line. Preferred embodiments use a meander resistor line made of polysilicon within a silicon integrated circuit. Simple processing mask modifications can be used to change the geometry of the meander line to vary the resistance. The wiping point is digitally selected.

Abstract: An integrated circuit wherein remapping logic permits the output-driver characteristics of a given pin to changed in software, by changing the data stored in a nonvolatile control bit.

Abstract: An electronic key which includes a pseudo-random number generator. If the correct password is received, the contents of a secure memory will be outputted by the electronic key. However, if an incorrect password is received, that password will be used as a seed value for the pseudo-random number generator, and the resulting value will be outputted.Thus, if a copier exercises the key through all possible passwords, the incorrect passwords, as well as the correct password, will result in the same output data every time it is tried.

Abstract: A system which includes a microprocessor (or microcontroller) and an auxiliary chip which monitors the system power supply voltage and performs related functions for the microprocessor. In one mode of operation (for use with a low-power CMOS processor), the auxiliary chip sends an interrupt to the microprocessor when the power supply falls to a first level, and also resets the microprocessor when the supply voltage reaches a second preset level on the way up (i.e. while power is being restored). In a selectable second mode of operation (for use with NMOS processor), the auxiliary chip resets the processor when the power supply is on the way down.

Abstract: A digital to analog converter, wherein a time/voltage array is programmable, to determine which of the possible reference voltages will be enabled by which of the control inputs. Anther set of programmable options, in an output connection matrix, determines which of the internal voltage lines will be connected to which output lines. After the output connection matrix, output selection logic is used to determined which class of output levels are to be used. The output selection logic also preferably includes polarity-reversal gates, so that the polarity of a bipolar output can be reversed.

Abstract: An interface for current mode to Manchester encoded serial signals includes symmetric positive/negative doublet pulse generation. The doublet pulse generator provides a pulse duration held constant by feedback and a voltage/current reference and a minimal gap between the positive and negative polarity pulses by using the same signal to both turn off the positive pulse driver and turn on the negative pulse driver. Fault detection by sensing of asymmetry in received pulse uses a comparator with both high and low threshold input devices to provide minor asymmetry tolerance.

Abstract: Arbitration logic is provided to receive conflicts between a timekeeping system and a user system which share a common memory. The common memory is comprised of an array of dual memory cells, each of which has a timekeeping cell and a user cell and circuitry for transferring data from the timekeeping cell to the user cell or from the user cell to the timekeeping cell. User data is written into the user cells when it is available and immediately thereafter is transferred from the user cells to the timekeeping cells. Data from the timekeeping system is inhibited from being written into the timekeeping cells if, during the present update cycle of the timekeeping system, the user writes data into the common memory.

Abstract: A waveform generating circuit, wherein a master clock signal is fed into a tapped string of adjustable delay lines, and the tapped delay outputs are used to control selection of scaled voltage fractions for output. The use of adjustable delay lines means that very high time-domain resolution can be achieved, simply by making a small adjustment to the value of a trimmable capacitor.

Abstract: A low-power low-voltage CMOS six-transistor static random access memory (SRAM), which can operate on a power supply voltage which is less than the sum of the NMOS and PMOS threshold voltages, does not include any analog or metastable sense amplifier stages. The selected cell is allowed to pull one of its bitline pair all the way down to ground. Thus, full logic levels appear on the bitline pair. Only one line of the bitline pair is connected to the following gate stage. Perferably bitline percharge transistors are connected to always pull up any unselected bitline pair.

Abstract: A battery-backed ancillary power-management chip, in combination with a battery-backed microprocessor or microcontroller, permits a low-power system to achieve a zero-power standby mode with full nonvolatility. The ancillary chip contains transmission gates which can cut off the connection between two other chips if one of them is turned off. This avoids problems of power leakage, substrate pumping, etc., when two chips which are connected together can be independently powered up or powered down.Also provided is a portable data module, which includes a microprocessor and a large LCD display. The disclosed inventions permit the user to operate the display without powering up the microprocessor (to preserve a complex display, e.g. when the user has provided no inputs for a certain length of time), or to operate the microprocessor without the display (e.g. for data transfer or reduction operations).

Abstract: A battery-backed integrated circuit, with a double diode structure connected to signal lines. In the double diode structure, a first junction is three-dimensionally enclosed by a second junction, so that minority carriers generated at the first junction will be collected at the second junction. Thus, when a negative transient voltage appears on the signal line, the first junction can be forward biassed to source the needed current from ground, with minimal minority carrier injection.

Abstract: An integrated circuit timekeeper, which uses a hybrid hardware/software architecture, wherein the least significant bits are updated in hardware and the more significant bits are updated in software. This hybrid architecture provides improved power efficiency, layout efficiency, and flexibility in reconfiguration.

Abstract: A system which includes a microprocessor (or microcontroller) and an auxiliary chip which monitors the system power supply voltage and performs related functions for the microprocessor, and also provides a watchdog function to monitor the microprocessor's activity. The auxiliary chip itself can put to sleep by the microprocessor to minimize power consumption. The sleep mode of the auxiliary chip saves power by shutting down many of the input-sensing circuits, and the watchdog function. The sleep command is not accepted unless it stands in the proper timing relationship to a signal on the strobe pin. This permits the power savings of the sleep mode to be realized, without any risk of the system being placed in the sleep mode due to an out-of-control system condition.

Abstract: A battery management chip which controls charging and discharging currents of a rechargeable battery. In a portable module, the battery manager chip controls the charging and discharging of the rechargeable battery which powers the whole module, and is therefore connected directly to the battery and to the source of charging current. The chip is also connected to draw very small amounts of current from a third, stable battery, preferably a lithium battery, which is not necessarily rechargeable.

Abstract: An integrated circuit which uses vertical current flow through arsenic-implanted oxide films to provide low-current loads. These load elements provide a compact four-transistor SRAM which has very simple fabrication and very low power consumption.

Abstract: An embedded framing bit pattern in a serial bit stream is located by combining the last bit to arrive of the serial bit stream with a predetermined number of prior bits of the serial bit stream which are spaced apart by the pitch of the bits of the framing bit pattern, and this combination of the bits is tested to determine if the combination matches part of the framing bit pattern. If a match does not occur, then the bits which were combined together are changed to a bit pattern that will not result in a match when these bits (except for the eldest bit which is disregarded) is combined again with a new bit of the serial bit stream, no matter what the logic state of the new bit. In this manner all of the bits, as they arrive and are combined and tested, will eventually be changed except the bits which are part of the framing bit pattern.