Patents Assigned to David Sarnoff Researach Center
  • Patent number: 5581778
    Abstract: A parallel computing system comprising N blocks of processors, where N is an integer greater than 1. Each block of the N blocks of processors contains M processors, where M is an integer greater than 1. Each processor includes an arithmetic logic unit (ALU), a local memory and an input/output (I/O) interface. The computing system also contains a control means, connected to each of the M processors, for providing identical instructions to each of the M processors, and a host means, coupled to each of the control means within the N blocks of processors. The host means selectively organizes the control means of each of the N blocks of M processors into at least two groups of P blocks of M processors, P being an integer less than or equal to N. In operation, the host means causes the control means within each group of P blocks of M processors to provide each group of P blocks of M processors respectively different identical processor instructions.
    Type: Grant
    Filed: April 4, 1995
    Date of Patent: December 3, 1996
    Assignee: David Sarnoff Researach Center
    Inventors: Danny Chin, Joseph E. Peters, Jr., Herbert H. Taylor, Jr.