Abstract: A system monitoring device has the capacity of displaying historical or real time information and also allows a user to set, via direct manipulation, a range of values in relation to other currently displayed information in graphical format on a computer screen and to view such relationships in an intuitive manner. A user interface is provided so a user can interact with information being viewed via an input device, e.g., a pointing device. The user interface of the system monitoring device of the present invention includes two interactive icons allowing a user to select and display information contained in a historical record, or log, of information, as well as real time information, and also to expand the interactive icon into a range of values, specifying a minimum and maximum, so that there is a range between the point at which the activity may take place and the point at which the activity is canceled which a user can directly manipulate in an intuitive manner on a display device.

Abstract: A multiple layer interconnect structure for a semiconductor chip includes a graded transition layer of tungsten and a Group VIII metal, such as palladium, platinum or nickel (Pd, Pt or Ni) which allows formation of a Group VIII metal interconnect on a conventional pad of Al or Al alloy. The graded transition layer is interfaced between a thin adhesion layer on the pad and the Group VIII metal interconnect, and is approximately 100% tungsten where it interfaces the adhesion layer and approximately 100% Group VIII metal where it interfaces the interconnect layer. The tungsten in the graded transition layer acts as a solder barrier and the Group VIII metal interconnect is compatible with the silicon substrate so that packaging processing steps, including lead soldering, can be carried out, and the chip electrically tested, in the semiconductor fabrication facility.

Abstract: A set associative cache using decoded data element select lines which can be selectively configured to provide different data sets arrangements. The cache includes a tag array, a number of tag comparators corresponding to the maximum possible number of sets, a data element select logic circuit, and a data array. The tag and data arrays each provide, in response to an input address, a number of output tag and data elements, respectively. The number of output tag and data elements depends upon the maximum set size desired for the cache. An input main memory address is used to address both the tag and data arrays. The tag comparators compare a tag field portion of the input main memory address to each element output from the tag array. The select logic then uses the outputs of the tag comparators and one or more of the input main memory address bits to generate decoded data array enable signals. The decoded enable signals are then coupled to enable the desired one of the enabled data elements.