Abstract: A processing system on an integrated circuit includes a group of processing cores. A group of dedicated random access memories are severally coupled to one of the group of processing cores or shared among the group. A star bus couples the group of processing cores and random access memories. Additional layer(s) of star bus may couple many such clusters to each other and to an off-chip environment.

Abstract: A serially interfaced massively parallel Random Access Memory (RAM) includes a matrix of control logic sections on one integrated circuit die, augmented by a switching matrix with an external interface to multiple high speed serial signaling means. A matrix, of the same dimension, of dense memory element arrays is implemented on a different integrated circuit die. One control logic section die and one or more others containing memory sections are joined by appropriate means to form one integrated circuit stack, implementing a matrix of independent memory units. The switching matrix translates command and data content encoded on the external signaling means bidirectionally between internal data and control signals and connects these signals to the control logic sections. Each independent memory unit ably performs atomic read-alter-writes to enable software mutual exclusion operations (MUTEXes). Each and every matrix may guard against defects by having additional rows and/or columns.