Abstract: A power factor correction (PFC) converter comprises an inductor, a main switch, a voltage divider, a diode, and a controller. The main switch controls the inductor performing magnetization and demagnetization, wherein a voltage difference between two ends of the main switch is a switch voltage. The voltage divider divides the switch voltage and generates a division voltage. The controller performs the following operations periodically in general mode: turning on the main switch; turning off the main switch after the main switch is turned on for a period of time; obtaining the switch voltage according to the division voltage, and determining the period of time for which the main switch is turned on next time according to the switch voltage and a predetermined output voltage of the PFC converter; and obtaining an output voltage according to the switch voltage during a period of time after the main switch is turned off.

Abstract: A circuit for Flyback switching power supply includes a transformer having a primary winding, a secondary winding and an auxiliary winding, a power switch coupled to a dotted terminal of the primary winding, and a switch. A first terminal of the switch is connected to a non-dotted terminal of the auxiliary winding through a capacitor, a second terminal of the switch and a dotted terminal of the auxiliary winding are connected, respectively, to a ground. A common node of the capacitor and the auxiliary winding is configured to connect to a non-dotted terminal of the primary winding. A control circuit is configured to generate, based on a voltage at the common node of the capacitor and the auxiliary winding, a control signal to control the switch in order to achieve zero voltage switch (ZVS) of the power switch.

Abstract: A semiconductor Schottky rectifier built in an epitaxial semiconductor layer over a substrate has an anode structure and a cathode structure extending from the surface of the epitaxial layer. The cathode contact structure has a trench structure near the epi-layer and a vertical sidewall surface covered with a gate oxide layer. The cathode structure further comprises a polysilicon element adjacent to the gate oxide layer.

Abstract: An apparatus includes a capacitive device configured to provide bias power for a high-side switch, a gate drive path having variable resistance connected between the capacitive device and a gate of the high-side switch, wherein the gate drive path having variable resistance is of a first resistance value in response to a turn-on of the high-side switch, and the gate drive path having variable resistance is of a second resistance value in response to a turn-off of the high-side switch, and wherein the second resistance value is greater than the first resistance value, and a control switch connected between the gate of the high-side switch and ground.

Abstract: Signal transmission cables and serial interfaces with built-in signal boosting are provided. In some implementations, a signal transmission cable or interface for boosting signals comprises boosting circuitry. The boosting circuitry may comprise at least one boosting capacitor configured to be operatively coupled to a voltage supply during a charging phase and configured to be operatively coupled to the at least one line of a signal transmission cable or interface during a discharging phase, wherein, during the discharging phase, the at least one boosting capacitor boosts a voltage of the one or more signals transmitted on the at least one line. The boosting circuitry may comprise switching circuitry configured to switch the at least one boosting capacitor between from being operatively coupled to the voltage supply to being operatively coupled to the at least one line of the signal transmission cable or interface.

Abstract: A switched mode power supply (SMPS) includes a first switch, a second switch connected, at a switching node, in series with the first switch, and an inductor coupled between the switching node and an output node for providing an inductor current, at the output node. The SMPS also includes an oscillator circuit for providing a clock signal characterized by an oscillating frequency, an adaptive minimum duty-cycle circuit configured to receive an error voltage signal and to generate a current signal to vary the oscillating frequency of the clock signal in response to the error voltage signal, wherein the error voltage signal is based on an output signal at the output node, and a pulse-width modulation (PWM) circuit configured to receive the error voltage signal and the clock signal and to provide a switching control signal to control the first switch and the second switch.

Abstract: An output driver with slew rate control includes an output transistor that includes a control terminal coupled to a switching input signal, a drain node coupled to the output node for coupling to a load device, and a source node coupled to a reference voltage. The output driver also has a slew control circuit including a current source coupled in series at a connection node with parallelly connected first switch transistor and second switch transistor. The connection node is coupled to the control terminal of the output transistor. The first switch transistor has a control terminal coupled to the switching input signal. The second switch transistor has a control terminal that is coupled to either the switching input signal or a dynamically modulated switching input signal, depending on a current direction at the output node.

Abstract: A method for forming a semiconductor Schottky rectifier device includes providing a semiconductor substrate, forming a hard mask for trench etch including openings for guard rings, an anode region, and a cathode region, and etching semiconductor epitaxial material layer to form a plurality of trenches. The method also includes forming a first dielectric layer and depositing a polysilicon layer, performing an anisotropic etch of the polysilicon layer to form polysilicon elements on sidewalls of the trench, and depositing and etching a second dielectric layer to expose a Schottky diode region and a bottom region of the trench in the cathode region. The method further includes depositing a first metal layer and performing a thermal treatment to form metal silicide in the Schottky diode region and the cathode region and forming a second metal layer and separating the second metal layer into an anode electrode and a cathode electrode.

Abstract: Systems and methods for signal boosting in serial interfaces are provided. In some implementations, a system for boosting signals comprises boosting circuitry. The boosting circuitry may comprise at least one boosting capacitor configured to be operatively coupled to a voltage supply during a charging phase and configured to be operatively coupled to the at least one line of a signal transmission line during a discharging phase, wherein, during the discharging phase, the at least one boosting capacitor boosts a voltage of the one or more signals transmitted on the at least one line. The boosting circuitry may comprise switching circuitry configured to switch the at least one boosting capacitor between from being operatively coupled to the voltage supply to being operatively coupled to the at least one line of the signal transmission line.

Abstract: A split-gate trench device chip has an active region in which a plurality of active trenches are disposed. The active region is enclosed by termination trenches disposed in a termination region, which extends to the edges of the chip. A gate metal lead is disposed on the device surface. The gate metal lead makes contact to gate electrodes in the active trenches through contact holes disposed in the active region. A source or a drain metal lead is also disposed on the surface. The source or the drain metal lead makes contact to the field plate electrodes through contact holes disposed outside the active region. Each active trench in the active region has a first end merge into a first termination trench and a second end separated from an adjacent second termination trench.

Abstract: Disclosed are some examples of Phase interpolator circuitry used in retimer systems. The phase interpolator circuitry includes a phase interpolator configured to: receive the phase control signal, generate, based on the phase control signal, an output clock signal, and provide the output clock signal to the transmitter to track a plurality data packets. Phase interpolator circuitry is coupled with clock data recovery circuitry. In some implementations, clock data recovery circuitry is coupled between a receiver and a transmitter. The clock data recovery circuitry is configured to: extract a data component from an input data signal associated with the receiver, provide the data component to the transmitter, and generate a phase control signal.

Abstract: A semiconductor structure includes a substrate having a first surface and a second surface opposite to the first surface. The semiconductor structure also includes a first diffusion layer disposed in the substrate and adjacent to the first surface, and a first electrode layer disposed on the first diffusion layer. The semiconductor structure further includes a second diffusion layer disposed in the substrate and adjacent to the second surface, and a plurality of diffusion regions disposed in the second diffusion layer. The semiconductor structure further includes a second electrode layer disposed on the second diffusion layer and in contact with the plurality of diffusion regions. The second diffusion layer is coupled to the plurality of diffusion regions through the second electrode layer. The substrate is sandwiched between the first electrode layer and the second electrode layer.

Abstract: Disclosed are a packaging substrate, a grid array package, and a preparation method therefor. The packaging substrate comprises a plurality of packaging units, and each packaging unit is defined by a closed packaging line. The packaging substrate comprises: a base substrate having a first surface and a second surface that are opposite to each other, a plurality of solder pads provided on the first surface, and a metal layer provided on the second surface. In a given packaging unit, the metal layer comprises a plurality of lead pads, at least one lead pad extending from an inner side of the packaging unit defined by the packaging line to an outer side. The lead pad is connected to one solder pad by means of a connecting member penetrating through the base substrate, and an orthographic projection of the connecting member on the base substrate at least partially covers the packaging line.

Abstract: A semiconductor device and a lead frame. The semiconductor device comprises at least one semiconductor chip that is attached to a surface of a base island in a first plane, wherein a connecting rib is connected to the base island, and has a first part which is obliquely connected to the base island; the connecting rib has a second part, and the second part has a surface in a second plane; the second plane is parallel to the first plane and is a plane different from the first plane; the connecting rib has a branch part divided from the second part and the branch part has, in the second plane, a surface used for receiving a lead connected to the semiconductor chip; and the branch part has an edge which is distant from a first edge of the base island by a first distance.

Abstract: A method for a switched mode power supply (SMPS) includes providing an error voltage signal based on a difference between a sampled output voltage of the SMPS and a target voltage, and generating a clock signal characterized by an oscillating frequency; generating a switching control signal based on the error voltage signal and the clock signal using pulse-width modulation (PWM). The method further includes varying the oscillating frequency of the clock signal according to the error voltage signal in a current generating circuit, and applying the switching control signal to control the power switches of the SMPS.

Abstract: Disclosed are some examples of Phase interpolator circuitry used in retimer systems. The phase interpolator circuitry includes a phase interpolator configured to: receive the phase control signal, generate, based on the phase control signal, an output clock signal, and provide the output clock signal to the transmitter to track a plurality data packets. Phase interpolator circuitry is coupled with clock data recovery circuitry. In some implementations, clock data recovery circuitry is coupled between a receiver and a transmitter. The clock data recovery circuitry is configured to: extract a data component from an input data signal associated with the receiver, provide the data component to the transmitter, and generate a phase control signal.

Abstract: This application provides a process for making a circuit of a bipolar junction transistor (BJT). The switchable short in one implementation of the invention is formed in a semiconductor wafer. A collector region is formed in the semiconductor wafer and inside of the collector region, a first base region is formed. An emitter region is formed inside the base region to form the BJT. A drain region is also formed inside the base region adjacent to the emitter region. A gate is formed over a portion of the base region adjacent to the drain region and the emitter region. The gate is connected to the collection region.

Abstract: A power converter and control circuit are provided. The control circuit has a power controller for turning on the power switch to maintain a desired output voltage and mode selection switch provides a mode selection signal. Depending on the magnitude of an input voltage of the power converter, in which the mode selection circuit compares the input voltage of the power converter with a reference voltage, a modulation controller is configured to turn on a modulation switch to activate the capacitor according to the mode selection signal.