Patents Assigned to DMO SYSTEMS LIMITED
  • Patent number: 10365617
    Abstract: A system for auto defect screening using adaptive machine learning includes an adaptive model controller, a defect/nuisance library and a module for executing data modeling analytics. The adaptive model controller has a feed-forward path for receiving a plurality of defect candidates in wafer inspection, and a feedback path for receiving defects of interest already screened by one or more existing defect screening models after wafer inspection. The adaptive model controller selects data samples from the received data, interfaces with scanning electron microscope (SEM) review/inspection to acquire corresponding SEM results that validate if each data sample is a real defect or nuisance, and compiles model training and validation data. The module of executing data modeling analytics is adaptively controlled by the adaptive model controller to generate and validate one or more updated defect screening models using the model training and validation data according to a target specification.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: July 30, 2019
    Assignee: DMO Systems Limited
    Inventors: Jason Zse-Cherng Lin, Shauh-Teh Juang
  • Patent number: 9547745
    Abstract: A system includes a critical signature library for storing critical signature databases of chip design layouts in semiconductor manufacturing and a statistical model creator for creating statistical models based on the known problematic circuit patterns stored in the critical signature databases and a target specification based on deviation between physical measurement and simulation data or design data associated with the known problematic circuit patterns. The system further has a statistical model based predictor for predicting and discovering unknown problematic circuit patterns by applying the statistical models to a large number of candidate circuit patterns generated from a random layout generator, or extracted from the chip design layout based on hot spot sites determined by extended lithographic process check on the chip design layout or inspecting wafers manufactured with the chip design layout with an aggressive sensitivity setting.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: January 17, 2017
    Assignee: DMO Systems Limited
    Inventors: Shauh-Teh Juang, Jason Zse-Cherng Lin
  • Patent number: 9142014
    Abstract: A number of wafers of a same semiconductor device are inspected to generate a plurality of candidate defect lists for identifying systematic defects. Each candidate defect list comprises a plurality of candidate defects obtained from inspecting one of the wafers. Each candidate defect is represented by a plurality of defect attributes including a defect location. The candidate defects in every one or more candidate defect lists are processed as a set by stage one grouping and filtering to generate a stage one defect list for each set. The candidate defects in all the stage one defect lists are then processed together by stage two grouping and filtering to generate a final defect lists for systematic defects. The defect attributes of each defect and a design pattern clip extracted from a design database based on the defect location are used in the hierarchical grouping and filtering.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: September 22, 2015
    Assignee: DMO SYSTEMS LIMITED
    Inventors: Jason Zse-Cherng Lin, Shauh-Teh Juang
  • Patent number: 8938695
    Abstract: A number of wafers of a semiconductor device are inspected to generate a plurality of wafer inspection data. A method for identifying critical hot spots to improve lithographic process of manufacturing the semiconductor device uses design signature analytics according to the plurality of wafer inspection data with reference to the design data of the semiconductor device. Design signature analytics includes global alignment, full chip pattern correlation, pattern characterization and design signature inference. The global alignment compensates for the physical coordinate offsets between the chip design data and the wafer inspection data. The full chip pattern correlation uses multi-stage pattern matching and grouping to identify highly repeating defects as hot spots. Pattern characterization extracts the design patterns and design signatures of the highly repeating defects.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: January 20, 2015
    Assignee: DMO Systems Limited
    Inventors: Shauh-Teh Juang, Jason Zse-Cherng Lin
  • Publication number: 20140214192
    Abstract: A design-based manufacturing optimization (DMO) server comprises a distributed computing system and a DMO software module incorporating with a design scanner to scan and analyze design data of a semiconductor device for optimizing manufacturing of the semiconductor device. The DMO software module sets up a pattern signature database and a manufacturing optimization database, generates design-based manufacturing recipes, interfaces with manufacturing equipment through a manufacturing interface module, and interfaces with electronic design automation suppliers for the design data through a design interface module. The DMO server executes the design-based manufacturing recipes for manufacturing optimization.
    Type: Application
    Filed: January 25, 2013
    Publication date: July 31, 2014
    Applicant: DMO SYSTEMS LIMITED
    Inventors: Shauh-Teh Juang, Jason Zse-Cherng Lin