Abstract: This invention relates to mounting integrated circuits (IC) to multi-chip modules (MCM) or substrates. More specifically, it provides a method of mounting a semiconductor die such as a thin slice of Mercury Cadmium Telluride (MCT) to a silicon semiconductor substrate, a read-out integrated circuit (ROIC), using a thermoplastic to reduce stress on the MCT caused by mismatched Coefficients of Thermal Expansion (CTE). This process provides for an array of infrared photodetectors on a material such as MCT to be mounted to a read-out integrated circuit (ROIC) using the Vertical Integrated Photodiode (VIP) approach to FPAs, while allowing double sided interdiffusion of CdTe for surface passivation to reduce dark currents and improve performance, without the problems associated with mismatched coefficients of thermal expansion during high temperature processes.

Abstract: In one embodiment, a semiconductor structure is disclosed. The structure includes both a silicon and a cadmium telluride layer. Each may have a (100) lattice orientation. A plurality of buffer layers are disposed between the silicon layer and the cadmium telluride layer. Each of these buffer layers has a lattice constant which is greater than the lattice constant of the layer below it and less than the lattice constant of the layer above it. As examples, these buffer layers may comprise zinc sulfide, zinc selenide, zinc telluride or zinc tellurium selenide.

Abstract: This invention relates to mounting integrated circuits (IC) to multi-chip modules (MCM) or substrates. More specifically, it provides a method of mounting a semiconductor die such as a thin slice of Mercury Cadmium Telluride (MCT) to a silicon semiconductor substrate, a read-out integrated circuit (ROIC), using a thermoplastic to reduce stress on the MCT caused by mismatched Coefficients of Thermal Expansion (CTE). This process provides for an array of infrared photodetectors on a material such as MCT to be mounted to a read-out integrated circuit (ROIC) using the Vertical Integrated Photodiode (VIP) approach to FPAs, while allowing double sided interdiffusion of CdTe for surface passivation to reduce dark currents and improve performance, without the problems associated with mismatched coefficients of thermal expansion during high temperature processes.

Abstract: This is a monolithic infrared detector readout circuit for a capacitive sensing element 111 wherein a high gain preamplifier 115 is biased by a large bias element 113, e.g. on the order of 10.sup.12 ohms. The output of the preamplifier 115 is a band-limited by a low pass single-pole filter 117 having a high value resistive element 119, e.g. on the order of 10.sup.9 ohms, and then is clamped by a clamp circuit 131 to a stable reference in a manner that doubles the amplitude of the signal and minimizes low frequency bias shifts and fixed pattern noise. The output of the clamp circuit 131 is buffered by buffer 123 prior to being multiplexed by row address signals. The output from a multiplex switch 125 is then applied to the column line for output to a video circuit or the like.