Abstract: An N:1 data compression system for compressing data on N DS1 trunks carrying 4N channels is disclosed. Waveform encoding circuitry is coupled to the N DS1 trunks for compressing the DS1 data into x bits and producing both encoded data and control parameters, where x.ltoreq.8. The system further includes circuitry coupled to the waveform encoding circuitry for receiving the encoded data and control parameters, performing digital speech interpolation and producing data packets which may include encoded data and control parameters that are transmittable on a single DS1 trunk.

Abstract: A communications terminal interfaces a large number of potential individual telephone subscriber channels with a wide bandwidth, time multiplexed fiber optic or other type of trunk line. A time slot interchanger within the terminal assigns each of the subscriber channel time slots to one of the time slots in the trunk line signal. Data of the individual time slots of a frame of data of all channels is sequentially stored in a random access memory and then read out in a different sequence. A uniquely addressed location is provided in the memory for data of each individual channel. For cases where all channels are not being utilized, the system omits reading and/or writing data into the corresponding memory data locations not being used, thus saving power.

Abstract: A high-speed communication system (32) comprises a serial-to-parallel converter (38) for arbitrary converting a stream of serial data to a stream of arbitrarily aligned parallel data. A pattern detector (44) is coupled to the serial-to-parallel converter (38) for detecting a predetermined pattern from the stream of parallel data and generating a phase signal responsive to the detection of the pattern. An aligner (42) coupled to the pattern detector (44) generates an aligned stream of parallel data responsive to the phase signal.

Abstract: A digital switching network for providing simultaneous connections among user processors of processor-based communications equipment. The user processors act as originators and destinations of data communications packets. Packet data connections are through node controllers, which communicate with gateways, which are connected to a switching network via packet links. Control messages are communicated between node controllers, gateways, and an interchange control subsystem via various control message links. All control message processing and packet data transmissions are synchronized with a packet frame synchronization signal, and processing tasks performed by each of the network subsystems are pipelined so that they occur simultaneously. Service requests are queued in a central queue in the interchange control system. The synchronization and queueing simplify the control messages that are required to set up and release the connections.

Abstract: There is disclosed a press-fit pinless latching shroud. The latching shroud retains a connector to a pinfield with two flexible interlocking arms. The connector may be removed from the shroud by the user by disengaging the flexible arms from the connector. The latching shroud mounts to the pinfield by creating an interference fit between a portion of the pinfield and a series of matching holes in its base.

Abstract: A circuit is provided for detecting out-of-lock condition in a phase lock loop. The phase lock loop receives a first signal having a first frequency and a voltage controlled oscillator of the phase lock loop produces a second signal having a second frequency. The circuit comprises a first data flip-flop coupled to the phase lock loop for receiving the first signal and clocked by the second signal. The first flip-flop produces an inverted output of the first signal. A second flip-flop is coupled to the phase lock loop for receiving the second signal clocked by the first signal, and produces a non-inverted output of the second signal. Additionally, an EXCLUSIVE-OR gate is coupled to the first and second flip-flops for receiving the inverted and non-inverted output thereof and producing a signal indicative of an out-of-lock condition.

Abstract: There is disclosed a press-fit pinless latching shroud. The latching shroud retains a connector to a pinfield with two flexible interlocking arms. The connector may be removed from the shroud by the user by disengaging the flexible arms from the connector. The latching shroud mounts to the pinfield by creating an interference fit between a portion of the pinfield and a series of matching holes in its base.

Abstract: Apparatus for packing and unpacking DS1 trunks comprises a packing circuitry for receiving compressed data from a plurality of DS1 trunks, packing the compressed data into the space of one DS1 trunk, and providing a serial output of data for the packed DS1 trunk. An unpacking circuitry is further provided for receiving data from a packed DS1 trunk, unpacking the data into the space of a plurality of DS1 trunks, and providing an output thereof.

Abstract: An integrated echo canceling multiplexor is provided which comprises an echo canceler for receiving DS1 signals for canceling echo in the DS1 signal and producing an echo-free digital logic signal. A first performance monitor is coupled to the echo canceler for receiving the echo-free digital logic signal and determining the quality of the signal. A multiplexor-demultiplexor is further coupled to the echo canceler for receiving the echo-free digital logic signal and producing a DS3 signal. Additionally, a second performance monitor is coupled to the multiplexor-demultiplexor and receives the DS3 signal and determines the quality of the signal.

Abstract: There is disclosed a system and method for controlling the cross connect fields of a multi-locational switched network from a single location under control of instructions from the end users. The different cross connect fields of the entire switched network are controlled in response to instructions received by the controller from each end user. The instructions specify the period of time when the end user desires to establish certain connections through the network and also specify the band-width required during that period of time. The controller preassigns certain channels of the internetwork links and at the designated time period the connections are established. The end user is billed only for the time the links were actually assigned.

Abstract: Rudimentary digital speech interpolation apparatus for compressing data on a plurality of channels is disclosed, which includes circuitry for receiving data bits and control bits for each channel. The presence of silence on each channel is determined in response to the received data bits and zero bits are allocated for any silent channel in a frame structure. In addition, circuitry also allocates x bits per channel for the data bits in an non-silent channel in the frame. At least six bits per channel are also allocated for the control bits in the frame. 4N such frames are grouped to form a multi-frame.

Abstract: There is disclosed a system and method for controlling the cross connect field of a multi-locational switched network from a single location under control of instructions from the end users. The different crossconnect fields of the entire switched network are controlled in response to instructions received by the controller from each end user. The instructions specify the period of time when the end user desires to establish certain connections through the network and also specify the band-width required during that period of time. The controller preassigns certain channels of the internetwork links and at the designated time period the connections are established. The system is designed to provide cost accounting and auditing information pertaining to the reserved time for each end user on a link by link basis as well as for the time during which the links were actually used for communication.

Abstract: An apparatus for controlling the operational status of echo canceling in an echo canceler is disclosed. A digital signal processor (DSP) module (52) is configured to provide two bandlimited filters (66, 68). A CAT filter (66) detects the exclusive presence of a continuity assurance. Test (CAT) tone, and a disable filter (68) detects the exclusive presence of an echo canceling disable tone. Outputs from the DSP module (52) couple to a controller module (64), and a control output from the controller module (64) couples to an echo canceler module (54). The control output causes the echo canceler module (54) either to provide echo canceling or to bypass echo canceling. Upon detection of the CAT tone (106), the control module (64) enables echo canceling (88). After the CAT tone disappears (90), the control module (64) monitors the disable filter (68) to determine whether the disable tone is being transmitted (94). If the disable tone is detected, the control module (64) disables echo canceling (100).

Abstract: A switch (10) which uses optical signals propagating through an air media is disclosed. Transmitters (14a-14n) radiate light along projection openings (40) through a solid, opaque housing (12). The projection openings (40) parallel each other and substantially reside in a lower plane (32) within the housing (12). Periscopic plugs (30) reflect such light upward along an intermediate direction (38) within the plugs (30) and out from the plugs (30) into incidence openings (42). The incidence openings (42) parallel each other and substantially reside in an upper plane (34) within the housing (12). Optical receivers (16a-16n) receive light propagating in the incidence openings (42). The incidence openings (42) reside substantially perpendicular to the projection openings (40).

Abstract: A method and apparatus for generating low level noise signals are provided. Two random numbers X.sub.1 and Y.sub.1 are first generated and bits 0-4 of the first random number X.sub.1 are extracted to produce a number X.sub.2. A number X.sub.3 is further computed by the formula: X.sub.3 =2.sup.-N (X.sub.2 .multidot.I), where N is a predetermined number and 1.ltoreq.I.gtoreq.2.sup.N -1. Bit 7 of the second random number Y.sub.1 is then extracted and combined as a sign bit with the computed number X.sub.3 to produce a sign-magnitude eight bit number W representing a sample of low level noise encoded in accordance with .mu.-law.

Abstract: A procedure for replacing an existing switch (62) with a greater-capacity replacement switch (12) in a communication system (10) is disclosed. The replacement switch (12) has redundant interconnect memories (40) that can store different interconnect maps. The replacement switch (12) also has logic circuitry (48) that forces the replacement switch (12) to operate using only a selected one of the redundant interconnect memories (40). The procedure loads a transparent map into the interconnect memories. Next, the procedure couples the replacement switch (12) in series between drop facilities (14) and the existing switch (62) and between the existing switch (62) and line facilities (16). The coupling scheme and transparent map route communication through both the replacement switch (12) and the existing switch (62) without substantially affecting service.

Abstract: A time slot interchange matrix is comprised of a plurality of matrix modules (50-56) each for receiving data on a plurality of channels and transmitting data on the same number of channels. Each of the modules consists of separate banks of random access memory that are interfaced with an intramatrix bus (70) for receiving data from each of the matrix modules in the system for storage therein during a collection frame. During a transmission frame, this information is randomly accessed in accordance with an interconnect pattern stored in a control RAM (122) for output from the digital matrix module. Each digital matrix module stores all of the information in the system such that the system is non-blocking for any given channel stored such that information is not impeded by the interconnect pattern of another digital matrix module. A digital bridge (80) is provided for collecting the information during a collection frame and then accumulating the information in a bridge IC circuit (137) as a conference.

Abstract: A message transport network (10) is provided for high speed switching between processing elements (72, 80). Clusters of low speed processing elements (72) may be connected to the message transport network (10) through a transport node controller (78). The transport node controller (78) and the high speed processors (80) are connected to the gateways (82). A pair of gateways (82) may be connected through a transport interchange node (106) to allow communication between processors (72, 80) associated with the gateways (82). A transport interchange supervisor (98) maintains a record of the status of each gateway (82) and generates commands to form connection between gateways (82) in the transport interchange node (106). A maintenance controller (102) and system maintenance processor (76) oversee the validity of the data being passed through the system on paths independent of the data transfer paths.

Abstract: A switching system (10) configured in a ring topology (14) is disclosed. The system (10) causes one or more 125 microsecond isochronous frames (20) to circulate in the ring (14) at any given instant in time. A delay circuit (22) temporarily saves an oldest one of the isochronous frames (20) until a youngest one of the isochronous frames (20) has completed its transmission. Consequently, an integral number of isochronous frames (20) circulate in ring (14). The isochronous frame (20) is partitioned to support a random access tunnel channel (26) and a plurality of independently controlled cells (28), which provide a variety of deterministic access services. Each cell (28) contains a control field (30) that contains sufficient information to specify the type of switching service provided by the cell (28) and various service parameters. A time multiplexer (42) separates the tunnel channel (26) from the cells (28).

Abstract: A time slot interchange matrix is comprised of a plurality of matrix modules (50-56) each for receiving data on a plurality of channels and transmitting data on the same number of channels. Each of the modules consists of separate banks of random access memory that are interfaced with an intramatrix bus (70) for receiving data from each of the matrix modules in the system for storage therein during a collection frame. During a transmission frame, this information is randomly accessed in accordance with an interconnect pattern stored in a control RAM (122) for output from the digital matrix module. Each digital matrix module stores all of the information in the system such that the system is non-blocking for any given channel stored such that information is not impeded by the interconnect pattern of another digital matrix module. A digital bridge (80) is provided for collecting the information during a collection frame and then accumulating the information in a bridge IC circuit (137) as a conference.