Abstract: Method for reconstruction of a three-dimensional model of an osteo-articular structure of a patient, wherein a) bi-dimensional patient-specific image data (41) of said structure is provided; (d) a preliminary solution, corresponding to a previously established solution model of the structure, is provided (42) from a base (21), said preliminary solution comprising a priori knowledge of the corresponding structure, previously established from structures of the same type, said preliminary solution comprising surface data describing the coordinates of the surface of the solution model, and bulk data describing at least one characteristic of the inside of the solution model; the preliminary solution is modified (42?, 43, 44, 46, 47, 48) to be brought in concordance with said patient-specific image data.
Type:
Grant
Filed:
October 31, 2008
Date of Patent:
September 22, 2015
Assignees:
Ecole National Superieure D'Arts Et Metiers (ENSAM), Ecole De Technologies Superieure
Inventors:
Jacques A. DeGuise, Benoit Godbout, Thierry Cresson, Ramnada Chav, Dominic Branchaud, Wafa Skalli, David Mitton
Abstract: The present invention relates to a Voltage-Controlled Oscillator (VCO) and to use of the VCO in a high-temperature sensor transceiver. The VCO has a voltage input and a frequency of oscillation dependent on the voltage input. The VCO includes a transistor providing a gain allowing for a sustained oscillation. The transistor also has a capacitance that varies as a function of the voltage input. The high-temperature sensor includes a high-temperature sensor operatively coupled to the VCO for wireless transmission of an output signal of the sensor.
Abstract: A system for Vddq integrated circuit (IC) testing is described herein. The systems teaches the positioning of a resistive element between a voltage source and the power supply terminal of the IC under test and the approximation of the voltage value at the power supply terminal when the IC is generally in a steady state. Depending on the approximated voltage value, the IC under test may be determined faulty or not.