Abstract: A signal voltage level dual clamping circuit is disclosed for use in a receiving circuit for extraction of timing information from a signal. A first, start-up voltage level clamp is provided, the operation of which is independent of the signal timing information. A second, gated voltage level clamp is provided, the operation of which is dependent on the signal timing information. A switching circuit operates to switch the first clamp out of operation and switch the second clamp into operation once sufficient timing information has been extracted from the signal to permit operation of the second clamp.
Abstract: A composite synchronization extraction circuit is particularly suited for receiving composite video signals containing closed captioning data in raster scan line 21 by means of a signal CMOS integrated circuit device. A dual mode voltage clamp is realized in CMOS technology. The clamp includes temperature compensated current sources in the form of complementary current mirrors through which a clamped composite synchronization node of is charged and discharged, the output of which controls a transistor for charging the composite synchronization node. Detected pulse amplitude is set by slicing the incoming pulse at the back porch level and then doubling the amplitude with an amplifier and comparing that level with the back porch level as derived from a sample-and-hold device. The slice voltage level is maintained without an off-chip capacitor by an analog-digital-analog conversion process.
Abstract: A data and synchronization extraction circuit for processing composite video signals containing closed captioning data is disclosed. A dual mode voltage clamp is realized in CMOS technology which includes temperature compensated current sources in the form of complementary current mirrors. A modified version of such current sources is also disclosed which permits trimming of the current after manufacture and packaging. Sync pulses are separated by doubling the amplitude of a composite video signal with an amplifier and comparing the amplified signal with a back porch level derived by a sample-and-hold device. Frequency and phase synchronization is accomplished by a combination of a frequency lock loop and a phase lock loop working in concert to generate a control voltage for a voltage controlled oscillator in a flywheel mode. The voltage controlled oscillator provides a clean source of timing information for the circuit.
Type:
Grant
Filed:
March 2, 1992
Date of Patent:
April 4, 1995
Assignees:
EEG Enterprises, Inc., Extratek, Inc.
Inventors:
Eric B. Berman, Apparajan Ganesan, William B. H. Jorden, Philip R. McLaughlin, William Posner
Abstract: The present invention is directed to the implementation of a reliable data communications system using the horizontal scan lines of video signals, and is particularly concerned with the minimization of problems which are caused as a result of false acquisition of horizontal scan lines and missed or dropped lines. In accordance with the present invention, a two-tier approach to receiving data transmitted via television signals is used. The two-tier approach includes a search mode and a lock mode. The present system operates on the principle that if a horizontal scan line (or lines) has been perfectly identified to contain data for successive fields of a video signal, then this scan line (or lines) can be presumed to be a valid data bearing scan line (or lines) in fields of the video signal yet to be received. The lock mode is then utilized to favor the retrieval of what would otherwise be missed or dropped horizontal scan lines were the system operating in the more restrictive search mode.
Type:
Grant
Filed:
March 26, 1990
Date of Patent:
March 26, 1991
Assignees:
PBSE Enterprises, Inc., EEG Enterprises, Inc.
Inventors:
Hermann J. Helgert, Mark S. Richer, William Posner
Abstract: An encoding technique for data that enables the data to be reliably transmitted via television signals, even when impulse noise may be present, uses a two-fold approach for forward error correction. As a first step, the data is assembled into blocks of suitable length and each block is encoded with an error correcting code to enable individual bit errors to be identified and corrected at the receiving end. In addition, the blocks of data are interleaved over several different lines of information. Each line of information is transmitted during the vertical blanking interval in a respective field of a video signal. At the receiving end, the individual lines of data are reassembled into the blocks of information. If impulse noise or other disruptions cause one of the lines to be lost, the result at the receiving end would only be the loss of one bit of data in each block. The error correcting code with which each block is encoded enables this individual bit error to be identified and corrected.
Type:
Grant
Filed:
March 11, 1988
Date of Patent:
September 11, 1990
Assignees:
PBS Enterprises, Inc., EEG Enterprises, Inc.
Inventors:
Mark S. Richer, Aderemi A. Adeyeye, Hermann Helgert