Abstract: This disclosure describes an operand file, a device that combines the functions of a register file, a reservation station, and a rename buffer into single storage element. The advantage of this mechanism is that it eliminates copying results and operands between the register file, reservation station, and rename buffer, thereby greatly simplifying the design and reducing area and power consumption. Furthermore, it can also be used in multithreaded processors that spawn children threads by copying some or all of the parent thread's registers to each of the children thread's registers.

Abstract: A dynamic PLA (DPLA) that combines registers and dynamic PLA to make the array “reprogrammable” after the array is built is disclosed. The DPLA comprises at least one logic plane; and at least one reprogrammable evaluate module within the at least one logic plane. The at least one reprogrammable evaluate module includes a first program input, a second program input, a storage element coupled to the first and second program inputs, and an input pass transistor whose gate is coupled to the output of the storage element and whose source and drain are coupled to a control input and the gate of an evaluate transistor. In such a DPLA, the AND plane and OR plane are fully populated with reprogrammable evaluate modules such that every input signal can be programmed to affect every AND term output and every AND term signal can be programmed to affect every OR term output.

Abstract: A caching device using an N-way replacement mechanism is disclosed. The replacement mechanism comprises at least one replacement order list with N positions, with the first-to-replace position at one end and the last-to-replace position at the opposite end, each position containing a way number, N way comparators, a control unit, a replacement order generator, and receiving a hit signal and, in case of a hit, a hit way number. A system and method in accordance with the present invention provides a programmable replacement mechanism applicable to caching devices, such as instruction and data caches and TLBs (translation lookaside buffers) in processors or texture map caches in graphics systems, that use set associative or fully associative organization. A replacement order list is maintained that specifies the order of which the elements in a set are to be selected for replacement.

Abstract: Dynamic PLAs are used as the basis of constructing a new class of programmable devices called field-programmable dynamic logic arrays (FPDLAs). Unlike existing programmable devices that use static logic, the FPDLAs use reprogrammable, reconfigurable, and fixed-function dynamic PLAs in programmable modules that provide both programmable logic and interconnect structures. A system of micro clocks is used to ensure that each dynamic PLA operates correctly by allowing it to start the evaluate phase after all of its inputs have become valid. Since dynamic PLAs with large number of inputs can be built in a small area due to its regular circuit structure, and they produce the outputs in a time independent of the number of inputs affecting the outputs, FPDLAs can operate at a higher speed and require a smaller area than programmable devices built using static logic.

Abstract: A method and system for controlling refresh of a plurality of dynamic random access memory (DRAM) cells in a data processing system is disclosed. The method and system comprises of providing at least one valid bit to control the refresh of at least one row of DRAM cells and providing a set of commands by a software program to control the at least one valid bit. Accordingly, a system and method in accordance with the present invention allows for software control of a DRAM refresh to reduce power consumption in a data processing system. In a system and method in accordance with the present invention, a plurality of valid bits are provided, each valid bit allows for a group of DRAM cells to suppress the refresh operation when a refresh is not needed. Each of the valid bits controls the refresh of all cells in a row of DRAM cells and all cells of a memory location are contained in one row.

Abstract: A self-adjusting multi-speed pipeline in accordance with the present invention is disclosed. A self-adjusting multi-speed pipeline is aware of the required processing time of the slowest among the stages that are actually used in each cycle and to adjust the clock speed accordingly. Intelligence is added to the pipeline to detect when one or more of slower pipeline stages are to be used in each cycle. A clock generator observes these detection signals and increases or decreases the clock period in each cycle to ensure that the slowest pipeline stage completes its processing. The biggest benefit of such a pipeline is improved performance since the pipeline can now operate more efficiently. The speed of the pipeline is reduced only enough for the slowest stage in each cycle to complete its processing.

Abstract: A configurable dynamic PLA in accordance with the present invention provides for multiple programs onto one dynamic PLA and allows one of the multiple programs to be selected at any given time, making the array “configurable” after the array is built. In addition, if the evaluate modules are made reprogrammable, the PLA is both configurable and reprogrammable. The capability to reprogram the array allows new functions to be realized after the array is built. The capability to configure the array allows any one of the preprogrammed functions—be it hardwired or reprogrammed—to be selected for each evaluation cycle. This is especially useful since reprogramming the array may take multiple cycles.

Abstract: A dynamic PLA (DPLA) that combines registers and dynamic PLA to make the array “reprogrammable” after the array is built is disclosed. The DPLA comprises at least one logic plane; and at least one reprogrammable evaluate module within the at least one logic plane. The at least one reprogrammable evaluate module includes a first program input, a second program input, a storage element coupled to the first and second program inputs, and an input pass transistor whose gate is coupled to the output of the storage element and whose source and drain are coupled to a control input and the gate of an evaluate transistor. In such a DPLA, the AND plane and OR plane are fully populated with reprogrammable evaluate modules such that every input signal can be programmed to affect every AND term output and every AND term signal can be programmed to affect every OR term output.

Abstract: A repairable dynamic programmable logic array (DPLA) is disclosed. The repairable DPLA comprises of AND and OR logic planes and redundant term generators in the logic planes. A redundant term generator comprises a plurality of reprogrammable evaluate modules so that each input to the logic plane can be programmed to affect the redundant term generator. For repairing a defective AND term generator, a redundant output select module connected to the output of the redundant AND term generator is added to each of the OR term generators, including the redundant OR term generators. To repair a defective AND term generator, the wired-NOR function programmed into the defective AND term generator is programmed into the redundant AND term generator. The redundant output select module is programmed to be affected by the redundant AND term output if the associated OR term generator is programmed to be affected by the defective AND term generator.