Abstract: A multi-timescale voltage regulation method based on source-grid-load-storage multi -terminal collaboration of a power distribution network is disclosed, which comprises: establishing, based on a Petri network, a multi-mode switching control model based on voltage security event trigger to realize effective control of a global voltage; establishing multi-objective optimization taking into account a source-storage-load regulation cost and a network transmission loss to realize collaborative and dynamic control of controllable resources of a source terminal, a load terminal and a storage terminal in each operating mode; and establishing a source-storage-load multi-terminal collaboration-based distributed voltage control model based on voltage security event trigger over a short timescale by taking into account the problems of voltage magnitude being out of limit and voltage leap, and solving online an optimal control sequence of the source terminal, the load terminal and the storage terminal in a receding horiz

Abstract: Disclosed are an emergency control method and system based on source-load-storage regulation and cutback. According to the method, output power of power generating sources is regulated according to a power regulating quantity and a frequency regulation requirement, an output power compensation and output frequency of each power generating source are maintained within permissible ranges, so that a balance between power supply and demand of a power distribution network is maintained; and standby energy-storage power stations are used to make up a power gap, and an external power supply system is used to assist in making up a power deficiency, so that large load disturbance can be handled make up the power gap.

Abstract: The present invention relates to a data synchronizing system and method using an XRI data link. The data synchronizing system includes a user data provider, a user data consumer, and an XRI resolver that analyzes received XRI identifiers and rovides metadata related to the XRI identifiers. The user data provider instructs the user data consumer to update data using the metadata related to the XRI identifiers, and provides a data synchronizing function, which has been provided in the form of a Web service, through the XRI data link. As a result, an application program can facilitate data synchronization, and thus the efficiency of a system can be improved.

Abstract: An adaptive interface providing apparatus and method of setting an individual degree of attention for a specific driver based on an average degree of attention are provided.

Abstract: A medium access control (MAC) technique of a multihop sensor network. In the multihop sensor network, the MAC technique may contribute to significantly reducing transmission delay, and allow real-time services to be provided to all nodes by extending a guaranteed time slot (GTS) restricted to one hop in a personal area network (PAN) coordinator (PNC) to all nodes. Furthermore, the MAC technique may allow the number of available GTSs to be significantly increased, by using all 16 frequency band channels instead of using only a single frequency band and setting a multi-superframe.

Abstract: A method for fabricating a semiconductor power integrated circuit includes the steps of forming a semiconductor structure having at least one active region, wherein an active region includes a well region for forming a source and a drift region for forming a drain region, forming a trench for isolation of the active regions, wherein the trench has a predetermined depth from a surface of the semiconductor structure, forming a first TEOS-oxide layer inside the trench and above the semiconductor structure, wherein the first TEOS-oxide layer has a predetermined thickness from the surface of the semiconductor device, forming a second TEOS-oxide layer on the first TEOS-oxide layer, wherein a thickness of the second TEOS-oxide layer is smaller than that of the first TEOS-oxide layer, and performing a selective etching to the first and second TEOS-oxide layers, to thereby simultaneously form a field oxide layer pattern, a diode insulating layer pattern and a gate oxide layer pattern, to thereby reduce processing step