Abstract: A duty cycle correction circuit comprises a duty cycle detector, a filter, a comparator, a SAR DAC, an equalization device, a pass gate circuit, and a duty cycle corrector. The duty cycle detector generates control signals in response to internal clock signals. The equalization device equalizes voltage levels of the control signals, and the pass gate circuit applies the control signals to the duty cycle corrector. The filter obtains average voltages of the control signals. The comparator compares output signals from the filter to generate a comparison result. The SAR DAC performs a SAR algorithm to generate analog output signals based on the comparison result. The duty cycle corrector receives external clock signals, the analog output signals, and output signals from the pass gate circuit to generate the internal clock signals with a corrected duty cycle.

Abstract: A circuit for sensing a multi-level cell (MLC) flash memory is disclosed. The circuit comprises a plurality of first decoding units, a second decoding unit and a data latch. Each of the first decoding units provides a timing information and includes a controlled transistor to allow a current to pass therethrough, and a capacitor to be charged by the current or to discharge through the controlled transistor. The second decoding unit provides a latch signal and includes a controlled transistor to allow a current to pass therethrough, the magnitude of the current being associated with data in an MLC, and a capacitor to be charged by the current or to discharge through the controlled transistor. The data latch, in response to the timing information from each of the first decoding units and the latch signal from the second decoding unit, determines the data in the MLC.

Abstract: A bandgap reference circuit includes a first circuit, a second circuit and a third circuit. The first circuit is for generating a first current and a first voltage according to a first reference voltage. The second circuit is coupled to the first circuit, for generating a second voltage according to the first voltage. The third circuit is coupled to the first circuit and the second circuit, for generating a voltage offset according to the first current, and generating a bandgap reference voltage according to the second voltage and the voltage offset. The first circuit and the second circuit complement each other for offsetting variations of the bandgap reference voltage due to temperature changes.

Abstract: A circuit for controlling leakage current in random access memory devices comprises a pre-charge equalization circuit. The pre-charge equalization circuit provides a pre-charge voltage to a pair of complementary bit lines of a memory cell of a random access memory device in accordance with a pre-charge signal. When the memory cell is in a self-refresh mode, the pre-charge signal is activated by a periodically triggered pre-charge request and also activated before and after the memory cell is self-refreshed.

Abstract: A semiconductor memory device includes memory cells, a sensing amplifier, a precharge circuit, and a control signal generator. The precharge circuit has a NMOS transistor and two PMOS transistors, and is used to precharge bit lines of a bit line pair, wherein the NMOS transistor is controlled by a first control signal, and the two PMOS transistors are controlled by a second control signal. The control signal generator is used to generate the first and second control signals, wherein the first control signal is at a logic high level only when the second control signal is at a first logic low level, the first control signal is at a logic low level when the second control signal is at a second logic low or a first logic high level, and the second logic low level is higher than the first logic low level.

Abstract: A circuit for sensing a multi-level cell (MLC) comprises a first switch associated with a first read bit, a second switch associated with a second read bit, a first switch control unit to control the first switch in response to a first data bit from a counter, and a second switch control unit to control the second switch in response to a second data bit from the counter.

Abstract: The present invention discloses a circuit for generating a dual-mode proportional to absolute temperature (PTAT) current. The circuit includes a voltage stabilizing circuit to provide a voltage reference, and a load current control circuit comprising a first transistor to provide a first load current based on the voltage reference, a second transistor to provide a second load current based on the voltage reference, a first switch to control whether to allow the first load current to flow therethrough in response to different predetermined temperatures, and a second switch to control whether to allow the second load current to flow therethrough in response to the different predetermined temperatures. A resultant current resulting from at least one of the first load current or the second load current has different current magnitudes at the different predetermined temperatures.

Abstract: A voltage regulator circuit comprises active and standby amplifiers, first and second transistors, and a capacitor. The active amplifier has a negative input connected to a first reference voltage, and the standby amplifier has a negative input connected to a second reference voltage. The first reference voltage is greater than the second reference voltage. The first transistor has a gate connected to an output of the active amplifier and a drain connected to a voltage regulated output, and the second transistor has a gate connected to an output of the standby amplifier and a drain connected to the voltage regulated output. The capacitor is connected between a chip enable signal and the voltage regulated output.

Abstract: A semiconductor memory device includes memory cells, a sensing amplifier, a precharge circuit, and a control signal generator. The precharge circuit has a NMOS transistor and two PMOS transistors, and is used to precharge bit lines of a bit line pair, wherein the NMOS transistor is controlled by a first control signal, and the two PMOS transistors are controlled by a second control signal. The control signal generator is used to generate the first and second control signals, wherein the first control signal is at a logic high level only when the second control signal is at a first logic low level, the first control signal is at a logic low level when the second control signal is at a second logic low or a first logic high level, and the second logic low level is higher than the first logic low level.

Abstract: The present invention discloses a circuit for generating a dual-mode proportional to absolute temperature (PTAT) current. The circuit includes a voltage stabilizing circuit to provide a voltage reference, and a load current control circuit comprising a first transistor to provide a first load current based on the voltage reference, a second transistor to provide a second load current based on the voltage reference, a first switch to control whether to allow the first load current to flow therethrough in response to different predetermined temperatures, and a second switch to control whether to allow the second load current to flow therethrough in response to the different predetermined temperatures. A resultant current resulting from at least one of the first load current or the second load current has different current magnitudes at the different predetermined temperatures.

Abstract: A data input device for use in a memory device to avoid false data being written due to a postamble ringing phenomenon in a write operation is provided. The data input device comprises a buffer, a combinational logic circuit and a flip-flop unit. The buffer receives the data and outputs internal data to the flip-flop unit. The combinational logic circuit receives an external data strobe signal to generate a first data strobe signal and a second data strobe signal. The flip-flop unit stores the data in synchronization with the first data strobe signal and outputs the stored data in synchronization with the second data strobe signal. A last rising edge of the second data strobe signal is generated prior to onset of the postamble ringing on the external data strobe signal, so that a data transferred path in the flip-flop unit is closed prior to onset of the postamble ringing.

Abstract: A voltage regulator circuit for providing power management for a memory device is disclosed. The voltage regulator circuit comprises a voltage regulator and a switch circuit. The switch circuit includes a first oscillator to generate an oscillating signal, and a pulse generator to generate a pulse signal in response to the oscillating signal. The voltage regulator provides a current during standby mode of the memory device in response to the pulse signal. The current is smaller than one provided by the voltage regulator during normal mode of the memory device.

Abstract: An anti-fuse circuit including a programmable module, a read module, and a control module is provided. The programmable module has a plurality of data cells. The read module is coupled to the programmable module. During a normal operation, the read module distinguishes which one or more of the data cells are stressed. The control module is coupled to the programmable module. During a stress operation, the control module controls each stressed data cell to be coupled to a high voltage, a low voltage, and a control voltage. The first end of each stressed data cells is coupled to the low voltage, the second end of each stressed data cells is coupled to the high voltage, and the control end of each stressed data cells is coupled to the control voltage during the stress operation.

Abstract: A circuit for generating multiphase clock signals and corresponding indication signals is provided. The circuit includes a multiphase clock generation circuit, a DLL circuit, a timing circuit, and a phase comparison circuit. The multiphase clock generation circuit receives an external clock to provide a plurality of first clock signals, phases of which differ from one another. The DLL circuit receives the external clock signal to provide a second clock signal. The timing circuit receives the second clock signal and a comparison signal to provide a plurality of indication signals. Each of the plurality of indication signals has rising edges which lead the rising edges of a corresponding one of the first clock signals. The phase comparison provides the comparison signal if a delayed phase of the corresponding one of the indication signals is within a phase of one of the first clock signals.

Abstract: A semiconductor memory device with a self-refresh timing circuit is provided. The semiconductor memory device comprises a plurality of memory banks, a command decoder, a bank address generator, a self-refresh counter, and the self-refresh timing circuit. The self-refresh timing circuit comprises a temperature sensor, a reference voltage source, a comparison circuit, an enable circuit, and an oscillation circuit. The comparison circuit compares a voltage from the temperature sensor with a constant voltage from the reference voltage source and generates a comparison signal. The enable circuit activates the comparison circuit when self-refresh operations for at least one refresh row are completed in all memory cell banks. The oscillation circuit generates a self-refresh clock signal which controls the operating frequency of the bank address generator and the self-refresh counter.

Abstract: A data outputting method of a memory circuit is illustrated. The memory circuit having at least 16 data buffers DQ[0]˜DQ[15] for storing at least 16 batches of data is provided. If a quadruple data outputting mode is selected for the memory circuit, when the clock signal triggers the 16 data buffers DQ[0]˜DQ[15], the 4 batches of the data stored in the 4 data buffers DQ[0], DQ[1], DQ[8], DQ[9] via 4 input/output pins connected to the 4 data buffers DQ[0], DQ[1], DQ[8], DQ[9], the batch of data stored in the data buffer DQ[2n+2] is transferred to be stored in the data buffer DQ[2n], and the batch of the data stored in the data buffer DQ[2n+3] is transferred to be stored in the data buffer DQ[2n+1], for n is an integer from 0 through 2, and from 4 through 6.

Abstract: A semiconductor memory device with a self-refresh timing circuit is provided. The semiconductor memory device comprises a plurality of memory banks, a command decoder, a bank address generator, a self-refresh counter, and the self-refresh timing circuit. The self-refresh timing circuit comprises a temperature sensor, a reference voltage source, a comparison circuit, an enable circuit, and an oscillation circuit. The comparison circuit compares a voltage from the temperature sensor with a constant voltage from the reference voltage source and generates a comparison signal. The enable circuit activates the comparison circuit when self-refresh operations for at least one refresh row are completed in all memory cell banks. The oscillation circuit generates a self-refresh clock signal which controls the operating frequency of the bank address generator and the self-refresh counter.

Abstract: A method for controlling operations of a delay locked loop (DLL) of a dynamic random access memory (DRAM) is provided herein. A phase detector of the DLL compares an external clock signal with a feedback clock signal to generate a first control signal. A delay line circuit of the DLL delays the external clock signal according to the first control signal. A detector of the DRAM detects variations of the first control signal to determine a length of an enable period of an enable signal. The delay line circuit and the output buffer are active only during the enable period when the DRAM is in a standby mode.

Abstract: A novelty repairing method and circuit are provided by the embodiments of the present invention, wherein the input/output (IO) compression manner can be used therein to reduce the access time during the chip probing 1 (CP1) test, and each redundant column selected line (RCSL) can be divided into several partial redundant column selected lines (P-RCSLs) which are respectively responsible for repairing the defects of the corresponding regions. Based upon the repairing method, the memory circuit can reduce the number of the RCSLs. Furthermore, a variable region dividing manner is applied therein, so as to increase the probability for repairing the defect of the memory circuit.

Abstract: A dynamic random-access memory (DRAM) and a method for testing the DRAM are provided. The DRAM includes a memory cell, a bit line associated with the memory cell, a local buffer, and a bit line sense amplifier (BLSA). The local buffer receives a first power voltage as power supply. The local buffer provides a ground voltage to the bit line when a data signal is de-asserted and provides the first power voltage to the bit line when the data signal is asserted. The BLSA receives a second power voltage as power supply. The BLSA provides the second power voltage to the bit line when the data signal and a wafer level burn-in test signal are both asserted. The second power voltage may be higher than the first power voltage. The wafer level burn-in test signal is asserted when the DRAM is in a wafer level burn-in test mode.