Abstract: An LDD MOSFET structure in which gate sidewall spacers are formed of polycrystalline silicon and electrically shorted to the gate to extend gate control over the LDD region surface oxide and thereby reduce and control interface charge trapping without increasing substrate currents.
Type:
Grant
Filed:
April 25, 1988
Date of Patent:
September 19, 1989
Assignee:
Elite Semiconductor & Sytems International, Inc.