Abstract: An electronic assembly including a plurality of electrically conductive elements separated by insulative material and a digital FM demodulator circuit coupled to some of the electrically conductive elements. The FM demodulator circuit having an FM detector circuit and a DC drift reducing circuit. The FM detector circuit has a detector input and a detector output that is the output of a comparator that is AC coupled to the rest of the FM detector circuit, the detector input receiving an input signal. The DC drift reducing circuit is electrically coupled to the detector output of the comparator, the DC drift reducing circuit detecting a DC drift of the detector output, the DC drift reducing circuit being additionally coupled to an input of the comparator, the DC drift reducing circuit substantially eliminating DC drift at the output of the FM demodulator circuit.

Abstract: An electronic assembly having a phase locked discriminator circuit that includes a phase locked loop (PLL), a voltage controlled oscillator (VCO), a signal output integrator, and a direct current (DC) drift reducing circuit. The PLL has an input to receive an oscillating signal. The signal output integrator, the PLL and the VCO are all electrically coupled together. The DC drift reducing circuit is electrically coupled to the PLL, the signal output integrator and the VCO. The DC drift reducing circuit detects a DC drift of an output of the signal output integrator by comparing a frequency of the oscillating signal to the DC drift.

Abstract: An electrical assembly including a conductor arrangement and a dual resolution potentiometer electrically connected to the conductor arrangement. The dual resolution potentiometer includes a first resistive element having a first adjustment mechanism and a second resistive element having a second adjustment mechanism. The first adjustment mechanism being coupled in a hysteresis arrangement to the second adjustment mechanism.

Abstract: A feedback gate bias circuit for use in radio frequency amplifiers to more effectively control operation of LDFET, GaNFET, GaAsFET, and JFET type transistors used in such circuits. A transistor gate bias circuit that senses drain current and automatically adjusts or biases the gate voltage to maintain drain current independently of temperature, time, input drive, frequency, as well as from device to device variations. Additional circuits to provide temperature compensation, RF power monitoring and drain current control, RF output power leveler, high power gain block, and optional digital control of various functions. A gate bias circuit including a bias sequencer and negative voltage deriver for operation of N-channel depletion mode devices.

Abstract: An electrical assembly including a conductor arrangement and a multi-resolution potentiometer electrically connected to the conductor arrangement. The multi-resolution potentiometer includes a first resistive element having a first adjustment mechanism and a first wiper, and a second resistive element having a second adjustment mechanism and a second wiper. The first adjustment mechanism is coupled in a hysteresis arrangement to the second adjustment mechanism. A resistor network provides an electrical output for the potentiometer and electrically couples the first wiper with the second wiper.

Abstract: An electrical assembly including a conductor arrangement and a multi-resolution potentiometer electrically connected to the conductor arrangement. The multi-resolution potentiometer includes a first resistive element having a first adjustment mechanism and a first wiper, and a second resistive element having a second adjustment mechanism and a second wiper. The first adjustment mechanism is coupled in a hysteresis arrangement to the second adjustment mechanism. A resistor network provides an electrical output for the potentiometer and electrically couples the first wiper with the second wiper.

Abstract: An electrical assembly including a conductor arrangement and a dual resolution potentiometer electrically connected to the conductor arrangement. The dual resolution potentiometer includes a first resistive element having a first adjustment mechanism and a second resistive element having a second adjustment mechanism. The first adjustment mechanism being coupled in a hysteresis arrangement to the second adjustment mechanism.

Abstract: An electrical assembly including a conductor arrangement and a dual resolution potentiometer electrically connected to the conductor arrangement. The dual resolution potentiometer includes a first resistive element having a first adjustment mechanism and a second resistive element having a second adjustment mechanism. The first adjustment mechanism being coupled in a hysteresis arrangement to the second adjustment mechanism.

Abstract: An electrical assembly including a conductor arrangement and a dual resolution potentiometer electrically connected to the conductor arrangement. The dual resolution potentiometer includes a first resistive element having a first adjustment mechanism and a second resistive element having a second adjustment mechanism. The first adjustment mechanism being coupled in a hysteresis arrangement to the second adjustment mechanism.

Abstract: A feedback gate bias circuit for use in radio frequency amplifiers to more effectively control operation of LDFET, GaNFET, GaAsFET, and JFET type transistors used in such circuits. A transistor gate bias circuit that senses drain current and automatically adjusts or biases the gate voltage to maintain drain current independently of temperature, time, input drive, frequency, as well as from device to device variations. Additional circuits to provide temperature compensation, RF power monitoring and drain current control, RF output power leveler, high power gain block, and optional digital control of various functions. A gate bias circuit including a bias sequencer and negative voltage deriver for operation of N-channel depletion mode devices.

Abstract: A hydraulic jack including a frame and a pump connected to the frame. The pump includes a rod, a housing, a piston and a plurality of valves. The rod has a cross-sectional area. The housing has an end through which the rod slides. The piston is associated with said rod, with the piston establishing a rod side chamber and a piston side chamber within the housing. The piston having a cross-sectional area. The plurality of valves each are fluidly connected to the rod side chamber and/or the piston side chamber. The piston, the rod and the valves are arranged to provide a first hydraulic fluid flow associated with the cross-sectional area of the piston until a predetermined pressure is reached and a second hydraulic fluid flow associated with the cross-sectional area of the rod after the predetermined pressure is reached.

Abstract: Phase-locked oscillators (74, 152, 172, or 196) include both a digital integrator (82 or 146) and a digital lead compensator (84, 148, or 180), and use either analog (108) or digital (184) summation of integration and lead-compensation signals to provide a lead-compensated digital integrator (86, 150, or 182). Preferably, integration and/or lead compensation includes decoding UP and DOWN signals into plus one, minus one, and/or zero signals. The phase-locked oscillators (74, 152, 172, or 196) may include one or more nonlinear digital-to-analog converters (282, 292, 310, 340, or 370) for digital-to-analog converting the digital phase-locking information and the digital lead-compensation information.

Abstract: A frequency-hopping oscillator (72, 136, 170, or 190) includes a phase-locked oscillator (74, 152, 172, or 196). The phase-locked oscillator (74, 152, 172, or 196) includes both a digital integrator (82 or 146) and a lead compensator (84, 148, or 180), and uses either analog (108) or digital (184) summation of integration and lead-compensation signals to provide a lead-compensated digital integrator (86, 150, or 182). The frequency-hopping oscillator (72, 136, 170, or 190) is adaptive in that it develops channelizing voltage via analog components, such as a VCO 20 and an improved D/A converter 98. The improved D/A converter 98 is designed to prevent “holes” even if a larger number of bits are processed using low-precision resistors.

Abstract: Signal processing apparatus (410) includes a phase-locked oscillator (200, 236, 310, 330, 390), having a closed loop with both forward (204) and feedback (206) paths, that is a part of a larger closed loop (438). The larger loop (438) is phase locked to the phase-locked oscillator (200, 236, 310, 330, 390) by a signal derived from the larger closed loop (438) that modulates the feedback path (206), and by an output frequency of the phase-locked oscillator (200, 236, 310, 330, 390) that is delivered to the larger loop (438). Modulating the feedback path (206) either adds pulses to the feedback path (206) or removes pulses, thereby causing irregularities in the flow of pulses. A low-pass filter (210) in the feedback path (206) obviates these irregularities, thereby also obviating incidental frequency modulation (IFM) in the output of the phase-locked oscillator (200, 236, 310, 330, 390).

Abstract: A method for inserting an audio signal (132) into a composite video signal (10) having a front porch (24), a back porch (26 or 32), a horizontal sync pulse (20) with a leading edge (22), and a luminance portion (16) to provide an audio-on-video signal (222), includes removing one or more video parts (180, 200) at least partially from the luminance portion (16), sampling one or more audio parts (182, 202), biasing a zero magnitude (238) of the audio parts (182, 202) to the midpoint (240) of the maximum luminance magnitude (242), and placing the sampled parts (182, 202) at least partially within the luminance portion (16) of the composite video signal (10) to form the audio-on-video signal (222).

Abstract: A D.C. modulated phase locked oscillator (60, 80, 100, 140, 160, 190, 220, 264, or 290) includes a phase locking oscillator (70, 90, 128, 180, 192, 222, 266, or 292) and a D.C. modulator (72, 92, 130, 156, 182, 194, 224, 268, or 294). Both a forward path (14) and a feedback path (16) are D.C. modulated. D.C.

Abstract: A D.C. modulated phase locked oscillator (220 or 264) is usable separately to provide an output that is both phase locked and D.C. modulated or is usable in a radio frequency receiver (200). The D.C. modulated phase locked oscillator (220or 264) includes a phase locking oscillator (222 or 266) and a D.C. modulator (224 or 268). Both a forward path (14) and a feedback path (16) are D.C. modulated. In one embodiment. D.C. modulation of the feedback path (16) includes using a modulation oscillator (64) and two flip-flops (228 and 164) to develop quadrature square waves, and using a quadrature phase shift keying (QPSK) mixer (234) to subtract a frequency of one of the square waves from the frequency in the feedback path (16). In another embodiment, D.C.

Abstract: A D.C. modulated phase locked oscillator (60, 80, 100, 140, 160, or 190) and a radio frequency receiver (200) that utilizes the D.C. modulated phase locked oscillator (60, 80, 100, 140, 160, or 190) both include a phase locking oscillator (70, 90, 128, 180, or 192) and a D.C. modulator (72, 92, 130, 156, 182, or 194). Both a forward path (14) and a feedback path (16) are D.C. modulated. D.C.