Abstract: A modulo arithmetic (61) for generating the addresses for accessing the memory cells of a memory in a DSP (digital signal processor) includes three inputs: an input address (30), an increment (31) and a modulo value (33). The next address (36) is generated based on these inputs as follows. An adder (22) generates a first address (32) by adding the input address (30) and the increment (31) and a second address (34) is generated by subtracting the modulo (33) from the first address (32) by means of the subtractor (23). The comparator (45) checks whether the second address is lower than or equal to zero and if so, the multiplexer (24) outputs the first address at its output (36). If the second address is higher than zero, the multiplexer (24) is controlled such that it outputs the second address (34). A further comparator (63) compares the input address (30) and the modulo (33).

Abstract: ADC circuitry has a first programmable gain amplifier to amplify an analog input, a first analog to digital converter coupled to an output of the first amplifier, a second programmable gain amplifier, to amplify the analog input, a second analog to digital converter coupled to an output of the second amplifier, and a digital circuit for deriving a digital output from the outputs of the first and second converters and a controller for controlling the gains of the first and second amplifiers, according to the outputs of the first and second converters. Such programmable gain pre amplifiers help enable effective dynamic range to be extended without unduly increasing the number of quantisation bits, or the number of components or the power dissipation. It can be used in applications sensitive to size and power, such as DSP based acoustic devices including hearing aids.

Abstract: A method and system for managing physiological systems is provided. The physiological system management (PSM) system includes one or more signal acquisition blocks to collect physiological information. The PSM system includes oversampled filterbanks for transferring one or more input signal related to the physiological information into subband signals, and a subband processing scheme for processing the outputs from the oversampled filterbanks for event detection in one or more physiological systems. The PSM system includes an adaptive controller which decides on the proper control measure and delivers the measure to the one or more physiological systems.

Abstract: A modulo arithmetic (61) for generating the addresses for accessing the memory cells of a memory in a DSP (digital signal processor) includes three inputs: an input address (30), an increment (31) and a modulo value (33). The next address (36) is generated based on these inputs as follows. An adder (22) generates a first address (32) by adding the input address (30) and the increment (31) and a second address (34) is generated by subtracting the modulo (33) from the first address (32) by means of the subtractor (23). The comparator (45) checks whether the second address is lower than or equal to zero and if so, the multiplexer (24) outputs the first address at its output (36). If the second address is higher than zero, the multiplexer (24) is controlled such that it outputs the second address (34). A further comparator (63) compares the input address (30) and the modulo (33).

Abstract: The invention deals with a controlling device (22) for an electrical device such as for example a hearing aid (20). The hearing aid (20) includes a power supply (23) and a functional unit (21) controlled by the controlling device (22) via a reset signal (2). In order to reduce undesired behaviour of the hearing aid in case of transients, brown-out or other oscillations of the input voltage (1), the controlling device (22) is built such that the functional unit (21) is resetted as long as the rising supply voltage (1) is lower than a startup threshold. Once the functional unit (21) is enabled, it remains enabled as long as the supply voltage (1) does not fall below a shutdown threshold where the shutdown threshold voltage is lower than the startup threshold voltage. This hysteresis is implemented via a reference generator (24) generating a constant reference voltage (27) and a modifiable voltage divider (28) which generates different output voltages (1.1) in dependency of the output of the comparator (25).

Abstract: A reference voltage generator according to the invention includes a sub circuit (10) for producing a first current (6) with a negative thermal coefficient, a sub circuit (30) for producing a second current (4) with a positive thermal coefficient, a summing circuit (20) for summing these currents (4, 6) and an output circuit (40) for generating a reference voltage (1) that is stable over temperature, supply voltage and fabrication processes. The critical path between Vdd (2) and GND (3) that delimits the minimum possible supply voltage in the summing circuit (20) includes a mirror transistor (21, 22) and a cascode transistor (23, 24). Since the mirror transistors and the cascode transistors are designed for working in weak inversion their saturation voltage is about 0.15 V. Accordingly, the minimum possible supply voltage is the sum of the reference voltage and the saturation voltage a mirror transistor and a cascode transistor. With a reference voltage between 0.4 V and 0.

Abstract: In a listening device such as for example a hearing aid (1) where an input signal (10) is received by a microphone (2), converted from analog to digital (3), digitally processed (4) including a conversion from a time domain into a frequency domain, converted from digital to analog (5) and transmitted to a user by means of a loudspeaker (6), the internal digital processing (4) generates an unwanted noise signal, the so called undesired periodic noise (12), at specific frequencies. The undesired periodic noise is coupled via ground and the battery (7) into the signal processing path. According to the invention, the undesired periodic noise is filtered out of the input signal (10.2) during the digital signal processing (4), after the conversion of the digital signal into the frequency domain.