Abstract: High density disc drive apparatus that packs a large number of disc drives into a computer cabinet. The disc drives are removably installed in disc cages mounted on shelves of a drawer that slides out the front of the cabinet. A linear actuator drives the drawer and a controller moderates the actuator to ensure smooth start-up and stopping of the drawer so selected disc drives can be replaced during computer operation without disturbing the operation of the remaining disc drives. Built-in pin connectors facilitate bringing I/O and power cables to the disc drives and the desired replacement.

Abstract: High density disc drive apparatus that packs a large number of disc drives into a computer cabinet. The disc drives are removably installed in disc cages mounted on shelves of a drawer that slides out the front of the cabinet. A linear actuator drives the drawer and a controller moderates the actuator to ensure smooth start-up and stopping of the drawer so selected disc drives can be replaced during computer operation without disturbing the operation of the remaining disc drives. Built-in pin connectors facilitate bringing I/O and power cables to the disc drives and the desired replacement.

Abstract: A plurality of processing units, each having a local memory connected thereto is disclosed. A write sense controller is also connected to each of the processing units to transmit a memory write word into a shared portion of local memory over a reflective memory line. Other write sense controllers receive the memory words from the reflective memory bus and cause them to be written into corresponding storage locations in the shared partitions of their local memories.

Abstract: Disclosed is a multiprocessor computer system including a plurality of processor modules with each of the processor modules including at least one processor and a cache memory which is shared by all of the processors of each processor module. The processor modules are connected to a system bus which comprises independent data, address, vectored interrupt, and control buses. A system memory which is shared by all the processor modules is also connected to the buses, and the cache memories in each processor module store those memory locations in the main memory most frequently accessed by the processors in its module. A system control module controls the operation and interaction of all of the modules and contains the bus arbiters for the vector, data and address buses. The system control module also controls the retrying of requests which are not completed and should any requester fail to obtain access to a bus, the system control module also unjams this deadlock.

Abstract: A real time data processing system in which each of a series of processing nodes is provided with its own data store partitioned into a first section reserved for the storage of data local to the respective node and a second section reserved for the storage of data to be shared between nodes. The nodes are interconnected by a data link and whenever a node writes to an address in the second section of a data store the written data is communicated to all of the nodes via the data link. The data in each address of the second sections of the data stores can be changed only by one respective processing node which acts as a master for that address. As each address containing shared data can only be written to by one node collisions between different nodes attempting to change a common item of data cannot occur.

Abstract: A caching system for a shared bus multiprocessor which includes several processors each having its own private cache memory. Each private cache is connected to a first bus to which a second, higher level cache memory is also connected. The second, higher level cache in turn is connected either to another bus and higher level cache memory or to main system memory through a global bus. Each higher level cache includes enough memory space so as to enable the higher level cache to have a copy of every memory location in the caches on the level immediately below it. In turn, main memory includes enough space for a copy of each memory location of the highest level of cache memories. The caching can be used with either write-through or write-deferred cache coherency management schemes.