Abstract: A cryptographic Serial ATA (SATA) apparatus comprises a main controller, a SATA device protocol stack, a SATA host protocol stack, and a cryptographic engine. The cryptographic engine is operatively coupled between the main controller and the SATA device and host protocol stacks and configured to provide high-speed cryptographic processing.

Abstract: A data encryption/decryption system comprising a cryptographic interface operatively coupled between a host device and a data storage device is disclosed. The host and data storage devices include respective IDE controllers supporting full ATA protocol. The cryptographic interface includes a host device-side IDE controller and a data storage device-side IDE controller, each controller supporting partial ATA protocol. The cryptographic interface also includes a cipher engine adapted to transparently perform real time data ciphering during IDE/ATA data transfer between the host and data storage devices in conjunction with the host device-side IDE controller and the data storage device-side IDE controller.

Abstract: A cryptographic device comprises a data stream interceptor, a main controller receiving input from the data stream interceptor, and a pair of data generating and storage controllers adapted to perform data transfer protocols with corresponding peer controllers of a data generating device and a data storage device, respectively, on command from the main controller. The cryptographic device further comprises a cipher engine programmed to transparently encrypt and decrypt data streams flowing between the data generating device and data storage device on command from the main controller. The cryptographic device does not utilize system resources associated with the data generating and storage devices during operation.