Patents Assigned to Eoplex Limited
  • Patent number: 10679954
    Abstract: A method of manufacture of an integrated circuit system includes: providing a semiconductor wafer with a bond pad; attaching a detachable carrier to the semiconductor wafer, the detachable carrier including a carrier frame portion and a terminal structure; removing the carrier frame portion with the terminal structure attached to the semiconductor wafer; and forming an encapsulation encapsulating the semiconductor wafer, the bond pad, and the terminal structure.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: June 9, 2020
    Assignee: EoPLex Limited
    Inventors: David G. Love, Philip Eugene Rogren
  • Patent number: 10612751
    Abstract: An electrical system includes: a first base structure; a second base structure spaced apart from and opposing the first base structure; a lens unit including a first end portion attached to the first base structure and a second end portion attached to the second base structure; a first light source attached to the first base structure and enclosed within the lens unit; and a second light source attached to the second base structure and enclosed within the lens unit.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: April 7, 2020
    Assignee: EOPLEX, LIMITED
    Inventors: Alex Shaikevitch, Sam Mahin Shirazi, Philip Eugene Rogren
  • Publication number: 20180047589
    Abstract: A lead carrier includes a temporary support layer, member, medium, or carrier upon which are dispersed a plurality of package sites, organized in a predetermined pattern such as a matrix or array. Each package site within a continuous sheet of mold compound of the lead carrier includes a semiconductor die; a set of terminal structures, each having a top side and an opposing back side that is exposed at a back side of the continuous sheet of mold compound; and a set of electrical current path redistribution structures, each formed as an elongate wiring structure having a first end, a second end distinct from the first end, a top surface, an opposing bottom surface, a width, and a thickness between its top and bottom surfaces. Each redistribution structure as-fabricated is either electrically pre-coupled to a predetermined terminal structure, or electrically isolated from each terminal structure.
    Type: Application
    Filed: May 4, 2016
    Publication date: February 15, 2018
    Applicant: EOPLEX LIMITED
    Inventor: Philip E ROGREN
  • Publication number: 20180047588
    Abstract: A lead carrier includes a continuous sheet of mold compound having a top side and an opposing back side, and forms an array of package sites corresponding to semiconductor packages. Each package site when fabricated includes a semiconductor die having a top side, and an opposing treated base exposed at the back side of the continuous sheet of mold compound; a set of terminal pads, each having a top side and an opposing back side exposed at the back side of the continuous sheet of mold compound; a plurality of wire bonds formed between a set of input/output junctions on the top side of the semiconductor die and the top side of each terminal pad; and hardened mold compound encapsulating the semiconductor die, the set of terminal pads, and the plurality of wire bonds. Each package site excludes a die attach pad to which the semiconductor die is fixed.
    Type: Application
    Filed: May 4, 2016
    Publication date: February 15, 2018
    Applicant: EOPLEX LIMITED
    Inventor: Philip E ROGREN
  • Publication number: 20180034038
    Abstract: A solid state electrochemical cell structure includes at least one integrated anode—current collector structure having a counterpart integrated cathode—current collector structure separated by an electrolyte layer. An integrated anode or cathode—current collector structure can be fabricated as a generally planar or planar layer structure having a surface area greater or much greater than its thickness, and which carries anode or cathode material composition, respectively, in which a current collector layer is enveloped, embedded, or encased; or a porous 3D mesh current collector structure in which an anode material composition or cathode material composition, respectively is enveloped, embedded, or encased by way of residing within a void volume fraction of the 3D mesh current collector structure. Integrated anode-current collector structures, cathode-current collector structures, and electrolyte layers can be fabricated by way of an additive manufacturing process (e.g., 3D printing).
    Type: Application
    Filed: June 3, 2016
    Publication date: February 1, 2018
    Applicant: EOPLEX LIMITED
    Inventor: Philip E ROGREN
  • Patent number: 9604411
    Abstract: A layer of a first powder is dispensed in a layer over a build plate. Binder is then selectively applied to hold portions of the layer of first powder together. Unbound first powder is then removed. A second powder is then dispensed in a layer over the build plate and portions of the bound first powder above the build plate. Binder is then selectively applied to hold portions of the second powder together. Unbound second powder is then removed. A third or more different powders can be similarly dispensed and bound to complete a multi-material layer. The process is then be repeated on a next subsequent layer. A curing radiation source can accelerate binding of powder together. Voids can be formed in portions of the layers by dispensing a fugitive material in portions of each multi-material layer. Mechanisms for implementing the printing process are also disclosed.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: March 28, 2017
    Assignee: EoPlex Limited
    Inventor: Philip E. Rogren
  • Patent number: 9184114
    Abstract: A lead carrier provides support for an integrated circuit chip and associated leads during manufacture as packages containing such chips. The lead carrier includes a temporary support member with multiple package sites. Each package site includes a plurality of terminal pads surrounding a die attach region. The pads are formed of sintered electrically conductive material. A chip is placed at the die attach region and wire bonds extend from the chip to the terminal pads. The pads, chip and wire bonds are all encapsulated within a mold compound. The temporary support member can be peeled away and then the individual package sites can be isolated from each other to provide completed packages including multiple surface mount joints for mounting within an electronic system board. Edges of the pads are contoured to cause the pads to engage with the mold compound to securely hold the pads within the package.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: November 10, 2015
    Assignee: EOPLEX LIMITED
    Inventor: Philip E. Rogren
  • Patent number: 8865524
    Abstract: A lead carrier provides support for an integrated circuit chip and associated leads during manufacture as packages containing such chips. The lead carrier includes a temporary support member with multiple package sites. Each package site includes a die attach pad surrounded by a plurality of terminal pads. The pads are formed of a sintered electrically conductive material. A chip is mounted upon the die attach pad and wire bonds extend from the chip to the terminal pads. The pads, chip and wire bonds are all encapsulated within a mold compound. The temporary support member can be peeled away and then the individual package sites can be isolated from each other to provide completed packages including multiple surface mount joints for mounting within an electronics system board. Edges of the pads are contoured to cause the pads to engage with the mold compound to securely hold the pads within the package.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: October 21, 2014
    Assignee: EoPlex Limited
    Inventor: Philip E. Rogren
  • Patent number: 8749035
    Abstract: A lead carrier provides support for a semiconductor device during manufacture. The lead carrier includes a temporary support member with multiple package sites. Each site includes a die attach pad surrounded by terminal pads. The pads are formed of multiple materials including a lower layer and a body portion. An upper layer can also be provided over the body portion. A chip is mounted upon the die pad and wire bonds extend from the chip to the terminal pads. These parts are all encapsulated within a mold compound. The body portion is preferably formed by providing a matrix of metal powder and a suspension medium at locations where the pads are to be located. Heat is applied to disperse the suspension medium and sinter the metal powder to form the body portion. After encapsulation the temporary support member can be peeled away and the package sites isolated from each other.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: June 10, 2014
    Assignee: EoPlex Limited
    Inventor: Philip E. Rogren
  • Publication number: 20140070391
    Abstract: A lead carrier provides support for an integrated circuit chip and associated leads during manufacture as packages containing such chips. The lead carrier includes a temporary support member with multiple package sites. Each package site includes a plurality of terminal pads surrounding a die attach region. The pads are formed of sintered electrically conductive material. A chip is placed at the die attach region and wire bonds extend from the chip to the terminal pads. The pads, chip and wire bonds are all encapsulated within a mold compound. The temporary support member can be peeled away and then the individual package sites can be isolated from each other to provide completed packages including multiple surface mount joints for mounting within an electronic system board. Edges of the pads are contoured to cause the pads to engage with the mold compound to securely hold the pads within the package.
    Type: Application
    Filed: September 5, 2013
    Publication date: March 13, 2014
    Applicant: EoPlex Limited
    Inventor: Philip E. Rogren
  • Publication number: 20140004663
    Abstract: A lead carrier provides support for an integrated circuit chip and associated leads during manufacture as packages containing such chips. The lead carrier includes a temporary support member with multiple package sites. Each package site includes a die attach pad surrounded by a plurality of terminal pads. The pads are formed of a sintered electrically conductive material. A chip is mounted upon the die attach pad and wire bonds extend from the chip to the terminal pads. The pads, chip and wire bonds are all encapsulated within a mold compound. The temporary support member can be peeled away and then the individual package sites can be isolated from each other to provide completed packages including multiple surface mount joints for mounting within an electronics system board. Edges of the pads are contoured to cause the pads to engage with the mold compound to securely hold the pads within the package.
    Type: Application
    Filed: September 3, 2013
    Publication date: January 2, 2014
    Applicant: EoPlex Limited
    Inventor: Philip E. Rogren
  • Patent number: 8525305
    Abstract: A lead carrier provides support for an integrated circuit chip and associated leads during manufacture as packages containing such chips. The lead carrier includes a temporary support member with multiple package sites. Each package site includes a die attach pad surrounded by a plurality of terminal pads. The pads are formed of a sintered electrically conductive material. A chip is mounted upon the die attach pad and wire bonds extend from the chip to the terminal pads. The pads, chip and wire bonds are all encapsulated within a mold compound. The temporary support member can be peeled away and then the individual package sites can be isolated from each other to provide completed packages including multiple surface mount joints for mounting within an electronics system board. Edges of the pads are contoured to cause the pads to engage with the mold compound to securely hold the pads within the package.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: September 3, 2013
    Assignee: EoPlex Limited
    Inventor: Philip E. Rogren
  • Patent number: 8491830
    Abstract: A print-forming method is disclosed which provides a method to engineer and design boundaries between the materials used in devices. The boundary includes primarily a first material on one side and primarily a second material on the other side. At least some of the second material is located on the first material side of the boundary and at least some of the first material is located on the second material side of the boundary in a precise pattern that achieve the objectives of the design. This approach is then extended to 3-dimensional shapes with any number of materials. Material properties that differ from each other thus do not exhibit an abrupt transition within the overall structure, but rather are accommodated within the boundary region. Various different exemplary boundary region configurations are disclosed, as well as techniques for optimizing this print-forming manufacturing within boundary regions.
    Type: Grant
    Filed: July 11, 2008
    Date of Patent: July 23, 2013
    Assignee: Eoplex Limited
    Inventor: Arthur L. Chait