Abstract: A layout parasitic extraction system. The present invention is a connectivity-based approach for extracting layout parasitics. The present invention creates a connectivity-based database, where geometries of a layout are organized by net. The present invention allows net-by-net extraction of layout parasitics using a connectivity-based database. Furthermore, a user can select a net or nets for extraction. The present invention outputs a database containing nets and their extracted layout parasitics. The present invention can create a netlist format file from a database containing nets and their extracted parasitics to allow back annotation of layout parasitics into a circuit schematic or for use for other software (possibly from a third-party).

Abstract: A method for accurately simulating the timing and power behavior of digital MOS circuits is provided. The method includes piece-wise linear modeling of transistors, dynamic and static construction of channel connected components, event driven simulation and current measuring capabilities for power supplies, grounds, and individual resistors and transistors.

Abstract: A method for accurately simulating the timing and power behavior of digital MOS circuits is provided. The method includes piece-wise linear modeling of transistors, dynamic and static construction of channel connected components, event driven simulation and current measuring capabilities for power supplies, grounds, and individual resistors and transistors.