Abstract: A method of forming a doped region in a III-nitride substrate includes providing the III-nitride substrate and forming a masking layer having a predetermined pattern and coupled to a portion of the III-nitride substrate. The III-nitride substrate is characterized by a first conductivity type and the predetermined pattern defines exposed regions of the III-nitride substrate. The method also includes heating the III-nitride substrate to a predetermined temperature and placing a dual-precursor gas adjacent the exposed regions of the III-nitride substrate. The dual-precursor gas includes a nitrogen source and a dopant source. The method further includes maintaining the predetermined temperature for a predetermined time period, forming p-type III-nitride regions adjacent the exposed regions of the III-nitride substrate, and removing the masking layer.

Abstract: A diode includes a substrate characterized by a first dislocation density and a first conductivity type, a first contact coupled to the substrate, and a masking layer having a predetermined thickness and coupled to the semiconductor substrate. The masking layer comprises a plurality of continuous sections and a plurality of openings exposing the substrate and disposed between the continuous sections. The diode also includes an epitaxial layer greater than 5 ?m thick coupled to the substrate and the masking layer. The epitaxial layer comprises a first set of regions overlying the plurality of openings and characterized by a second dislocation density and a second set of regions overlying the set of continuous sections and characterized by a third dislocation density less than the first dislocation density and the second dislocation density. The diode further includes a second contact coupled to the epitaxial layer.

Abstract: A vertical III-nitride field effect transistor includes a drain comprising a first III-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second III-nitride material coupled to the drain. The field effect transistor also includes a channel region comprising a third III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction, a gate region at least partially surrounding the channel region, having a first surface coupled to the drift region and a second surface on a side of the gate region opposing the first surface, and a gate contact electrically coupled to the gate region. The field effect transistor further includes a source coupled to the channel region and a source contact electrically coupled to the source.

Abstract: A semiconductor device includes a III-nitride substrate having a first conductivity type and a first electrode electrically coupled to the III-nitride substrate. The semiconductor device also includes a III-nitride material having a second conductivity type coupled to the III-nitride substrate at a regrowth interface and a p-n junction disposed between the III-nitride substrate and the regrowth interface.

Abstract: A vertical III-nitride field effect transistor includes a drain comprising a first III-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction. The field effect transistor also includes a channel region comprising a third III-nitride material coupled to the drift region, a gate region at least partially surrounding the channel region, and a gate contact electrically coupled to the gate region. The field effect transistor further includes a source coupled to the channel region and a source contact electrically coupled to the source. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride field effect transistor is along the vertical direction.

Abstract: A method of growing a III-nitride-based epitaxial structure includes providing a substrate in an epitaxial growth reactor and heating the substrate to a predetermined temperature. The method also includes flowing a gallium-containing gas into the epitaxial growth reactor and flowing a nitrogen-containing gas into the epitaxial growth reactor. The method further includes flowing a gettering gas into the epitaxial growth reactor. The predetermined temperature is greater than 1000° C.

Abstract: Embodiments of the invention include a III-nitride semiconductor layer including a first portion having a first defect density and a second portion having a second defect density. The first defect density is greater than the second defect density. An insulating material is disposed over the first portion. The insulating material is not formed on or is removed from the second portion.

Abstract: A method of reusing a III-nitride growth substrate according to embodiments of the invention includes epitaxially growing a III-nitride semiconductor structure on a III-nitride substrate. The III-nitride semiconductor structure includes a sacrificial layer and an additional layer grown over the sacrificial layer. The sacrificial layer is implanted with at least one implant species. The III-nitride substrate is separated from the additional layer at the implanted sacrificial layer. In some embodiments the III-nitride substrate is GaN and the sacrificial layer is GaN, an aluminum-containing III-nitride layer, or an indium-containing III-nitride layer. In some embodiments, the III-nitride substrate is separated from the additional layer by etching the implanted sacrificial layer.

Abstract: A method according to embodiments of the invention includes epitaxially growing a III-nitride semiconductor layer from a gas containing gallium, a gas containing nitrogen, and a gas containing indium. The concentration of indium in the III-nitride semiconductor structure is greater than zero and less than 1020 cm?3. A structure according to embodiments of the invention includes a super lattice of alternating first and second III-nitride layers. The first layers are more highly doped than the second layers. The average dopant concentration in the super lattice is less than 1020 cm?3.