Abstract: A data processing system including a buffer memory having a plurality of segments for storing data and a memory location pointer having a plurality of bits, where each of the memory location pointer bits corresponds to a respectively different one of the buffer segments. The data processing system includes a central processing unit that writes binary data values into the memory location pointer to indicate availability of each of the buffer segments. A direct memory access controller unit continually transfers blocks of data from a mass storage device into the available buffer segments as indicated by the memory location pointer. The DMA controller further changes the state of the binary values, corresponding to the segments into which the blocks of data were stored, to indicate that the segments are not available for data transfer.

Abstract: A computer that provides data to a video display using a bitmap display memory organization and bitplane addressing. Separate control is provided for two bitplane backgrounds and for eight reusable and easily movable sprites. Additional logic allows for dynamically-controllable interobject priority and collision detection among data in each of the bitplane backgrounds and sprites. A coprocessor provides for video beam-synchronized changes to data in registers, freeing the main processor for general purpose computing tasks. A block image transferer is provided to rapidly copy data in large blocks from one memory location to another. In hold-and-modify mode, color output circuitry holds the values for a previously displayed pixel while bitplane data modifies those values, allowing for simultaneous display of a greatly increased number of colors.

Abstract: A data processing system has a central processing unit, a memory for storing a plurality of data structures corresponding to a presentantion, and a display device. The display device has a display screen including a presentation area for displaying a presentation. Each one of the data structures includes an action identifier and a plurality of attributes. The process provides for receiving a one of the plurality of data structures of the presentation, analyzing the received data structure to determine an action to be performed in response to the action identifier of the data structure, and performing the action corresponding to the action identifier in accordance with a plurality of the attributes of the received data structure.

Abstract: A circuit which transforms image data between bit-plane data representations and multi-bit pixel representations includes a plurality of sequential logic elements arranged as a matrix having columns and rows. Data values representing bit-plane data are stored into the columns of the matrix according to a first scheme and data values representing multi-bit pixel data are stored into the columns of the matrix according to a second scheme. Data applied to the columns of the matrix is shifted along the rows until the matrix is filled. The converted data is then read out along the rows of the matrix.