Abstract: The circuit embodying the invention comprises a pointer memory memorizing J=16 decremented write pointers associated with J=16 buffer queues. A channelling word supplied conjointly to incoming data and indicating the buffer queue in which this data is to be written, addresses the corresponding decremented write pointer. The write pointer and the channelling word form a write address for a buffer memory used as a medium for the J=16 queues. A comparator detects equality between the write pointer and the read pointer and in this case inhibits the acceptance of the incoming data which would overlay data not yet read. Logic means associated with the comparator control the updating, by possible incrementation, of the write pointer values contained in the pointer memory, after each data read in the buffer queues. This circuit is particularly well suited for use in an asynchronous self-channelling packet time-division switching system.

Abstract: The coding and decoding devices embodying the invention are connected by two paths, a main path and an auxiliary path, of a variable rate digital transmission network. When the main path is capable of dispatching the totality of the information rate that the coding device is able to issue, only a main coder and a main decoder, respectively of the coding and decoding devices, are active. When the main path is not capable of dispatching the totality of the picture information, an auxiliary coder and an auxiliary decoder, respectively of the coding and decoding devices, are also active and the auxiliary path dispatches the part of the information rate that cannot be dispatched by the main path. A decoder and a subtracter are provided in the coding device so as to estimate the part of information not transmitted by the main path.