Abstract: Segmentation is added to a reduced instruction set computer (RISC) processor which supports paging. The arithmetic-logic-unit (ALU) is extended to allow for a 3-port addition so that the segment base can be added when the virtual address is being generated. Segment bounds checking is achieved by extending the paging system to allow for valid regions that are less than the full page size. Sub-page validity can mimic segmentation because a segment can be broken up into a number of full pages and one or more partially-valid pages at the segment boundaries. A page that is not wholly valid has an "event" on the page, and a memory reference to this page will either cause a software routine to be invoked to check the segment bound, or an extension to the TLB, called a sub-page validity buffer, is used to check if the reference was to a valid portion of the page. Events may also be defined for program watchpoints and defective memory locations.

Abstract: The number of steps to perform integer division is reduced by combining detection of a remainder overflow with the final remainder restore step. When the sign bit of the partial remainder flips during the restore step, then there is no remainder overflow. However, when the sign bit does not change, then a remainder overflow is signaled. For signed division, the final quotient before a final complementation is also examined. This quotient should be a positive number since the dividend is initialized to a positive number, and the divisor is added or subtracted at each iteration assuming that it was a positive number. If the final quotient is negative, then an overflow is signaled except in a special case. If the quotient is the minimum integer, MININT, the most-negative number representable, and the expected sign is negative, then an overflow has not occurred. MININT is detected by ORing together the low bits in the quotient.

Abstract: A master-slave cache system has a large, set-associative master cache, and two smaller direct-mapped slave caches, a slave instruction cache for supplying instructions to an instruction pipeline of a processor, and a slave data cache for supplying data operands to an execution pipeline of the processor. The master cache and the slave caches are tightly coupled to each other. This tight coupling allows the master cache to perform most cache management operations for the slave caches, freeing the slave caches to supply a high bandwidth of instructions and operands to the processor's pipelines. The master cache contains tags that include valid bits for each slave, allowing the master cache to determine if a line is present and valid in either of the slave caches without interrupting the slave caches. The master cache performs all search operations required by external snooping, cache invalidation, cache data zeroing instructions, and store-to-instruction-stream detection.

Abstract: Exponents are first combined together, in a way that varies with the type of floating point operation. A single intermediate exponent result is placed on an intermediate exponent bus. This intermediate exponent is adjusted upwards for any carry-out from the operation on the mantissas, or downwards for any cancellation of leading mantissa bits, producing the final exponent result. The intermediate exponent on the intermediate exponent bus is also compared to a single criteria which is used for all types of floating point operations. Thus the compare logic may be simplified because only a single set of criteria is used for all types of operations. Alternately, the criteria may be varied depending upon the degree of precision used by all operations. Because the intermediate exponent is used, separate exponent adders are not necessary for the prediction unit and the floating point unit. Compound floating point operations may require more complex logic for combining the exponents.

Abstract: A CPU pipeline is able to process instructions from a complex instruction set computer CISC instruction set and from a reduced instruction set computer RISC set. A mode register is provided to indicate whether RISC or CISC instructions are currently being processed. Two instruction decode units are used, one for each instruction set. Compound CISC instructions flow from the decode pipestage to the address generate stage, then to an operand cache stage, and finally to an algebraic execute stage before the results are written back to the GPR register. When the CPU switches to RISC mode by clearing a mode bit in the mode register, the pipeline is re-arranged for processing the simpler RISC instructions. Two outputs are provided for the RISC instruction decoder. The first output is for simple execute-type instructions, while the second output is for load/store-type instructions, and connects to the address generate pipestage, which generates an address for the operand cache stage.

Abstract: An address of any desired instruction in a super-scalar processor is generated using address tracking logic. A sequential address register in the last stage of the processor's pipelines holds the address of the last or oldest instruction in the pipelines. This register is updated with a target address when a branch instruction is actually taken. A pipeline valid array contains valid bits for the instructions in the pipelines, and also contains the lengths of the instructions for complex instruction sets having instructions that vary in length. The address of the desired instruction is calculated as the sum of a base address and an adjustment value. The base address is the address of the last instruction which is stored in the sequential address register when there are no intervening taken branches between the desired instruction and the last instruction in the pipelines.

Abstract: A mixed-modulo address generation unit has several inputs, preferably three. The unit can effectively add together a subset of these inputs in a reduced modulus, and simultaneously add this partial sum to a full-width input using a full modulus, the full modulus being greater than the reduced modulus. Reduced-width address components, such as 16-bit components with a 32-bit adder, are applied to the subset of inputs. The mixed modulo address generation unit sign-extends to 32-bits one input that includes a sign bit, the input being in the subset of inputs. Each input in the subset of inputs is applied to a carry-generate unit which signals if the partial sum is equal to or exceeds the reduced modulus. Under normal conditions, the full-modulus sum from the adder is output as a linear address.

Abstract: An arithmetic-logic unit (ALU) includes a Boolean logic unit and an integer logic unit, both of which are adapted to incorporate the sign extension function for immediate constants or reduced-width operands. The Boolean logic unit is constructed from 4:1 multiplexers (muxes), one mux for every bit in a full-width operand. The operands or constants are input to the select inputs for the muxes while signals representing the truth table for a predetermined Boolean operation are inputted to the four data inputs of each of the muxes. This allows for many different kinds of Boolean operations to be executed by the Boolean logic unit; each type of Boolean operation called for by an instruction opcode will have a corresponding set of truth table signals for input to the muxes. Sign-extension can be combined with the Boolean operation by using the sign bit of the reduced-width operand to select one of two modified sets of truth-table signals.

Abstract: A dual-instruction set central processing unit (CPU) is capable of executing instructions from a reduced instruction set computer (RISC) instruction set and from a complex instruction set computer (CISC) instruction set. Data and address information may be transferred from a CISC program to a RISC program running on the CPU by using shared registers. The architecturally-defined registers in the CISC instruction set are merged or folded into some of the architecturally-defined registers in the RISC architecture so that these merged registers are shared by the two instructions sets. In particular, the flags or condition code registers defined by each architecture are merged together so that CISC instructions and RISC instructions will implicitly update the same merged flags register when performing computational instructions.

Abstract: The CISC architecture is extended to provide for segments that can hold RISC code rather than just CISC code. These new RISC code segments have descriptors that are almost identical to the CISC segment descriptors, and therefore these RISC descriptors may reside in the CISC descriptor tables. The global descriptor table in particular may have CISC code segment descriptors for parts of the operating system that are written in x86 CISC code, while also having RISC code segment descriptors for other parts of the operating system that are written in RISC code. An undefined or reserved bit within the descriptor is used to indicate which instruction set the code in the segment is written in. An existing user program may be written in CISC code, but call a service routine in an operating system that is written in RISC code. Thus existing CISC programs may be executed on a processor that emulates a CISC operating system using RISC code.

Abstract: A bi-planar multi-chip package has die mounted on both sides of an insulating flexible carrier. The die are located in two parallel planes, with the flexible carrier located on a third plane between the two die planes. The die are mounted with the active circuit area facing each other on opposing sides of the flexible carrier. The carrier has conductive layers forming interconnect traces on both sides, and through-vias for connecting traces on opposite sides. The opposing die are mounted to the carrier with a solder-bump process with opposing pads located directly opposite each other. Vias are located in close proximity to the pads, between adjacent pads on the flexible carrier. Because the vias are between two adjacent pads, the interconnect length between two pads is on the order of the pad pitch. Thus opposing pads on the two die may be connected through the adjacent via with a small interconnect length.

Abstract: A memory cell has the read current from the bit lines isolated from the bistable storage latch in the cell. Internal nodes of the bistable storage latch control isolated gates of MOS read transistors which gate the read current from the bit lines to a local node within the memory cell. The read current is then switched to ground from the local node by a read switch transistor. The read switch transistor is gated by the read row line. The read current is isolated from the read row line because the read row line is only connected to the isolated gate of the read switch transistor. The read current is also isolated from the bistable storage latch since the read transistors are connected at their isolated MOS gates to the bistable's nodes. This isolation of the read current allows additional read ports to be added without disrupting the cell's stability or write performance.

Abstract: A static RAM memory is ideally suited for BiCMOS processes. As in standard CMOS memory cells, the cells have cross-coupled inverters that have more efficient n-channel transistors for the drive transistors, which pull a bit line low during a read operation. The weaker p-channel transistors are used for load transistors in the cross-coupled inverters, adding to cell stability while requiring no power. In contrast to prior-art cells, p-channel pass transistors are used. Common-emitter word-line drivers are also used that require a small input-voltage swing in comparison with the large word-line voltage swing. A low voltage on the word line selects a memory cell by causing p-channel pass transistors to conduct, coupling bit lines to the cross-coupled inverters in the memory cell. Power consumption is reduced since only one selected word line is at a low voltage, while the deselected word lines are at a high voltage.

Abstract: An arithmetic-logic unit (ALU) includes a Boolean logic unit and an integer logic unit, both of which are adapted to incorporate the sign extension function for immediate constants or reduced-width operands. The Boolean logic unit is constructed from 4:1 multiplexers (muxes), one mux for every bit in a full-width operand. The operands or constants are input to the select inputs for the muxes while signals representing the truth table for a predetermined Boolean operation are inputted to the four data inputs of each of the muxes. This allows for many different kinds of Boolean operations to be executed by the Boolean logic unit; each type of Boolean operation called for by an instruction opcode will have a corresponding set of truth table signals for input to the muxes. Sign-extension can be combined with the Boolean operation by using the sign bit of the reduced-width operand to select one of two modified sets of truth-table signals.

Abstract: Segmentation is added to a reduced instruction set computer (RISC) processor which supports paging. The arithmetic-logic-unit (ALU) is extended to allow for a 3-port addition so that the segment base can be added when the virtual address is being generated. Segment bounds checking is achieved by extending the paging system to allow for valid regions that are less than the full page size. Sub-page validity can mimic segmentation because a segment can be broken up into a number of full pages and one or more partially-valid pages at the segment boundaries. A page that is not wholly valid has an "event" on the page, and a memory reference to this page will either cause a software routine to be invoked to check the segment bound, or an extension to the TLB, called a sub-page validity buffer, is used to check if the reference was to a valid portion of the page. Events may also be defined for program watchpoints and defective memory locations.