Abstract: A semiconductor integrated circuit device is provided with an electrical interconnect system which is stable at high temperatures. The interconnect system employs refractory metal compounds which are electrically conductive, which form stable couples with silicon and compounds thereof, and which remain stable at temperatures exceeding approximately 500.degree. C.

Abstract: A line scan image sensor capable of operating at several different spatial sampling frequencies is provided by utilizing a line scanning array having sampling photoelements of different surface areas. The spatial sampling frequency of the sensor can be varied by selectively combining the charge packets generated by the individual photoelements. In a preferred embodiment, photoelements having two different surface areas are used, with the ratio of the smaller surface area with respect to the larger surface area being 1:.sqroot.2. A programmable amplifier is provided to normalize the outputs of photoelements having different surface areas so that a uniform illumination on different photoelements will produce a uniform response. The programmable amplifier can also be programmed to equalize the outputs of the sensor between the different spatial sampling frequency modes.

Abstract: A novel output stage is provided for producing a TTL output signal in response to the differential output signals from an ECL switch. The output stage includes a translator portion to shift the levels of the complementary signals produced by the ECL switch to the appropriate levels for use in driving a TTL output stage, a phase splitter circuit which is driven by the level shifted complementary output signals from the ECL stage and a single output lead. The currents through the level shifting transistors and resistors are controlled by a single current reference generator. The output signals from the translator circuit have voltage levels substantially independent of variations in the power supply voltage.

Abstract: To completely isolate an island of silicon, a trench is cut into an epitaxial layer to provide access to a differently doped buried layer. While suspending the portion of the epitaxial layer surrounded by the trench by means of an oxide bridge, the underlying region of the buried layer is etched away to form a cavity under the active area. This cavity, as well as the surrounding trench, is then filled with a suitable insulating material to isolate the active island from the substrate.

Abstract: An improved electron beam test probe apparatus and a method for use of said apparatus for use in measuring the potential in a specimen which enables measurements to be insensitive to local electric fields in the vicinity of the point at which the potential of the specimen is being measured. The apparatus consists of an electron beam for bombarding the specimen at the point at which the potential of the specimen is to be measured, a magnetic lens for collimating the secondary electrons emitted fom the specimen in response to this bombardment, and a detector system for measuring the energy distribution of the secondary electrons so collimated. Tubular electrodes are employed in the energy distribution detection system. These electrodes have significantly higher field uniformity and intercept a smaller fraction of the secondary electrons than wire mesh electrodes.

Abstract: A semiconductor chip package configuration and a method are disclosed for facilitating testing of the chip package and mounting of the chip package on a substrate by forming one or more lead alignment bars in interconnecting relation with adjacent leads on the chip package, the lead alignment bars being formed from a material providing electrical isolation between leads during testing of the chip package and for providing physical spacing between the leads both during testing and later mounting of the chip package on the substrate so as to prevent adjacent leads from inadvertent contact. Preferably, the lead alignment bars are formed from a high resistivity material selected to provide sufficient conductivity between the interconnected leads for minimizing electrostatic discharge conditions therebetween, the material being sufficiently non-conductive to permit functional and dynamic testing of the leads.

Abstract: A system which enables signals to be supplied at precisely desired times in an automatic test system. The apparatus includes a base delay memory which stores information related to a base time delay, while a vernier memory stores information relating to timing corrections to be made to the base time delay. The base delay memory controls a counter while the correction memory controls a vernier deskew apparatus for further delaying the output signal from the counter. To prevent carries from the vernier memory from influencing the base delay memory, the most significant bit of the vernier memory is of the same significance as the least significant bit of the base delay memory. The most significant bit of the vernier memory is also connected to drive the counter, in effect providing the counter with two least significant bits, and enabling a single base delay memory to control more than one signal timing paths.

Abstract: A memory system for storing and retrieving data sequences of symbols in response to a query sequence is disclosed. Each of the sequences is made up of three types of symbols, constants, delimiters, and variables. A data sequence is retrieved in response to a query sequence if the two sequence can be made identical by replacing the variables in each sequence by constants or combinations of constants and delimiters, the combinations beginning and ending with a delimiter. To reduce the time needed to search the memory for all data sequences corresponding to a given query sequence, multiple processing units are employed. In addition to carrying out rule-based searches, the memory system can efficiently retrieve all records containing a specified list of key words.

Abstract: An apparatus for reducing the write recovery time of a memory during a write operation is responsive to the detection of a write enable signal for causing the data being written into a selected memory cell to be immediately coupled out on the memory's corresponding output data line independent of the speed at which the data is actually written into the memory cell. The state of a cache memory element is set to reflect this data state such that when the write enable signal goes off, the cache memory element maintains the present state of said output data line. The cache memory element is overridden as the corresponding memory cell reaches a steady state condition at the end of the write operation.

Abstract: A subsystem component for use in an image processing system to compute a gray scale histogram function or various statistical functions relating to the coordinates of a region or regions in a binary image. A selected function is computed at the video rate of frame generation.

Abstract: A high precision digital to analog converter comprises the combination of an imperfect or low resolution digital to analog converter having an error function known in terms of orthonormal components and an error compensating device capable of generating correction terms which do not interact with one another. The correction terms are based on orthonormal components namely, the Walsh function components, of each signal level to be compensated. At most only one weighting value per bit is required, the combination of which will compenate for errors of any bit combination. In a specific embodiment employing feedforward compensation, the output of the low resolution converter and of the compensating device may be summed to produce a high performance, high precision converter with increased accuracy and resolution.

Abstract: An integrated circuit structure comprises a plurality of islands of semiconductor material (16-1 through 16-5) each island being separated from adjacent islands by a groove formed in annular shape around said island to laterally define the dimensions of each such island, an oxide (12, 14) formed over the surface of said grooves (13-1 through 13-6) and said islands and a selected glass (15) deposited on said oxide (14) in the grooves and over the top surface of said device, said glass having the property that it flows at a temperature beneath the temperature at which dopants in the islands of semiconductor material substantially redistribute, said selected glass (15) having a substantially flat top surface thereby to give said structure a substantially flat top surface.

Abstract: A temperature compensated sense amplifier is connected to the sense node of a memory array which is OR tied to the bit lines of the array. A PNP current mirror supplies voltage independent controlled current to the sense node. A level shifting stage is connected to the sense node to establish a threshold sensing level, and to switch on to steer the current into the amplifier stage. A compensation stage is connected to the level shifting stage and the amplifier stage to compensate for the .beta. factors of the transistors and the resistive changes with temperature. A temperature compensated current sink is connected to the PNP current mirror to track over temperature in opposition therewith and maintain a constant current into the sense node. The level shifting stage and the amplifier stage also include temperature compensating features to provide a sensing threshold which tracks constantly over the operating temperature range.

Abstract: A microprocessor with a multiplexer having its output coupled to the input of the instruction register for storing instructions to be executed and applying the bits of the instruction as the input signals to a mapping PLA. The inputs of the multiplexer are the information bus coupled to external pins to receive instructions either from external memory or from an external console, and the output of the ALU. The path from the output of the ALU to the input of the instruction register allows better self testing of the processor by iteself and self-generation of input/output instructions. This structure simplifies the processor by allowing console requests, instructions from memory and self generated instructions all to be stored in the same register, i.e., the instruction register, thereby eliminating the need for separate registers for each type of instruction.

Abstract: An electron beam test probe system for analyzing the operation of an integrated circuit is described. It includes a circuit for generating a test signal pattern and coupling the test signal pattern to the integrated circuit under test. It also includes an electron beam test probe for making potential measurements at specified points on the surface of the integrated circuit. These potential measurements can be displayed as an image of the surface of the integrated circuit or as a graph of the potential at a specified point on the surface of the integrated circuit as a function of time for times chosen with respect to the test signal pattern. The points at which potential measurements are made may be specified with reference to a schematic diagram of the integrated circuit. The schematic diagram may be inputted to the test probe system in a format which is consistent with that used by currently available circuit simulation programs.

Abstract: Structure is disclosed for a charge-coupled device for generating reference signals indicative of black and white optical conditions and for generating an end-of-scan indicator signal. The black reference signal is generated by electrically and optically isolating one or more photosites of the CCD. A white reference signal is generated by injecting a controlled amount of charge into one or more elements of a shift register of a charge-coupled device. The end-of-scan indicator signal is generated by injecting a signal into at least one element of a shift register which does not have photosites associated with it. The black and white reference signals allow the utilization of the full dynamic range of the device under a wide range of operation conditions, while the end-of-scan indicator eliminates the need for external counting or reset circuits associated with conventional charge-coupled devices.

Abstract: Information indicative discrete events of interest imbedded in raw data are globally classified, or filtered with respect to scale and changes in the scale of observation to effect intelligent perception of phenomena. Large scale components are classified as events while small scale components of an identified event designate points of occurrence of the event. The invention has broad application in artificial intelligence and signal processing wherein perceived discrete events, including minima, maxima, inflections, cusps, and discontinuities have a significance other than as noise. Methods and apparatus are described which utilize the subject invention in signal processing applications.

Abstract: A circuit technique for stabilizing the timing of signals at an output node of a gate, despite substantial variations in temperature. In a gate having a switching portion and an emitter follower, the temperature-dependence of the gate delay within the switching portion may be offset by suitable control of the temperature characteristics of the load current source supplying the emitter follower output node. The load current source comprises a current source resistor, a current source transistor having its collector coupled to the output node, and a reference voltage source. The voltage source, rather than having a zero temperature coefficient as in known temperature-compensated configurations, is configured to have a temperature coefficient chosen to provide a temperature dependence in the delay through the emitter follower that offsets the temperature dependence of the delay through the switching portion so that the total gate delay is substantially temperature-independent.

Abstract: The present invention utilizes the power available for application to a static RAM cell in a manner which provides efficient use of the power so that greater standby power may be applied to the static RAM to increase the memory speed. The current required to maintain the memory cell in a preset state flows from the U.sub.cc source through a row of parallel memory cells and through a common bias supply and various peripheral circuits, such as decoders. A shunt voltage regulator controls the dependence of the common bias supply voltage on current fluctuations caused by addressing and deaddressing the memory cells. The invention includes an isolation device for isolating a particular row of memory cells when it is addressed without disturbing the bias on other memory cell rows. Similarly, the reference voltages of each of the peripheral circuits can be made independent of the common bias supply voltage and independent of the other peripheral circuits by the use of a local voltage regulator on each peripheral.

Abstract: A programmable charge coupled device transversal filter 5 includes a charge coupled device register 10 for receiving and delaying incoming analog signals, a series of floating gate charge detectors 15, a corresponding number of sets of binary scaled capacitors C.sub.0, . . . 2C.sub.0 . . . 2.sup.n C.sub.0, an output circuit including a positive and negative bus coupled to a differential amplifier, and mask or otherwise definable electrical connections for connecting selected ones of the scaled sets of capacitors between the floating gate 15 corresponding to that set and one of the positive and negative buses 22 and 23.