Patents Assigned to Farichild Semiconductor Corporation
  • Patent number: 10026805
    Abstract: In at least one general aspect, a silicon carbide (SiC) device can include a drift region and a termination region at least partially surrounding the SiC device. The termination region can have a first transition zone and a second transition zone. The first transition zone can be disposed between a first zone and a second zone, and the second zone can have a top surface lower in depth than a depth of a top surface of the first zone. The first transition zone can have a recess, and the second transition zone can be disposed between the second zone and a third zone.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: July 17, 2018
    Assignee: Farichild Semiconductor Corporation
    Inventor: Andrei Konstantinov
  • Patent number: 7893779
    Abstract: A system reduces a received RF signal from EMI generated by a digital electronic system that includes a clock. In the present invention the clock frequency, that generates signals and strobes data out, is purposely changed or modulated, by, illustratively, driving the power node of the clock. The typical filter circuit between the clock power node and the power supply is used to advantage in that the filter impedance allows a buffer to more easily drive the clock power node since the low impedance of the power supply is isolated by the filter circuit. The changing of the clock frequency spreads the EMI RF harmonics over a spectrum so that any harmonics received by an RF receiver will be short lived and therefore of small magnitude.
    Type: Grant
    Filed: October 29, 2008
    Date of Patent: February 22, 2011
    Assignee: Farichild Semiconductor Corporation
    Inventors: Jim Morra, Seth Prentice
  • Patent number: 6855964
    Abstract: An ESD NMOS structure with an odd number of N-type structures built into a P-type well. Buried N-type structures are positioned between the N-type structures. The center N-type structure and each alternate N-type structure are electrically connected to each other, to the buried N-type structures, and to the output contact; while the other N-type structures are electrically connected to each other and the P-well and to ground. When a positive ESD event occurs, a depletion zone is created in the P-well between the N-type buried structures and the N-type structures thereby increasing the resistivity of the structure. Moreover, when a positive ESD event occurs, the lateral NPN transistors on either side of the center N-type structure break down and snap back. The resulting current travels through the area of increased resistivity and thereby creates a larger voltage along the P-well from the center N-type structure out toward the distal N-type structures.
    Type: Grant
    Filed: October 25, 2002
    Date of Patent: February 15, 2005
    Assignee: Farichild Semiconductor Corporation
    Inventor: Ronald B. Hulfachor